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| Order this document by MC68HC812A4/D Rev. 3.0 MC68HC812A4 Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice. NON-DISCLOSURE AGREEMENT HC12 REQUIRED Advance Information REQUIRED AGREEMENT NON-DISCLOSURE Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. (c)Motorola, Inc., 1999 Advance Information 2 MC68HC812A4 -- Rev. 3.0 MOTOROLA Advance Information -- MC68HC812A4 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 29 Section 2. Register Block . . . . . . . . . . . . . . . . . . . . . . . . 43 Section 3. Central Processor Unit (CPU12) . . . . . . . . . . 59 Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . 69 Section 5. Operating Modes and Resource Mapping . . 79 Section 6. Bus Control and Input/Output (I/O) . . . . . . . . 93 Section 7. EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Section 8. Memory Expansion and Chip-Select . . . . . 121 Section 9. Key Wakeups . . . . . . . . . . . . . . . . . . . . . . . . 143 Section 10. Clock Module . . . . . . . . . . . . . . . . . . . . . . . 153 Section 11. Phase-Lock Loop (PLL) . . . . . . . . . . . . . . . 167 Section 12. Standard Timer Module . . . . . . . . . . . . . . . 175 Section 13. Multiple Serial Interface (MSI) . . . . . . . . . . 213 Section 14. Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . 223 Section 15. Serial Peripheral Interface (SPI) . . . . . . . . 263 Section 16. Analog-to-Digital Converter (ATD) . . . . . . 285 Section 17. Development Support . . . . . . . . . . . . . . . . 305 Section 18. Electrical Characteristics . . . . . . . . . . . . . 321 Section 19. Mechanical Specifications . . . . . . . . . . . . 339 Advance Information MOTOROLA List of Sections MC68HC812A4 -- Rev. 3.0 3 List of Sections MC68HC812A4 -- Rev. 3.0 4 List of Sections Advance Information MOTOROLA Advance Information -- MC68HC812A4 Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 1.5 1.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Section 2. Register Block 2.1 2.2 2.3 2.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Section 3. Central Processor Unit (CPU12) 3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.4.1 Accumulators A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.4.2 Accumulator D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.4.3 Index Registers X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.4.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Advance Information MOTOROLA Table of Contents MC68HC812A4 -- Rev. 3.0 5 Table of Contents 3.4.5 3.4.6 3.5 3.6 3.7 3.8 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Section 4. Resets and Interrupts 4.1 4.2 4.3 4.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.5 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.5.1 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . .73 4.5.2 Highest Priority I Interrupt Register . . . . . . . . . . . . . . . . . .74 4.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.6.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.6.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.6.3 COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.6.4 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.7 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.7.1 Operating Mode and Memory Map. . . . . . . . . . . . . . . . . . . .76 4.7.2 Clock and Watchdog Control Logic . . . . . . . . . . . . . . . . . . .76 4.7.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.7.4 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.7.5 Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.7 Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.8 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 MC68HC812A4 -- Rev. 3.0 6 Table of Contents Advance Information MOTOROLA Table of Contents Section 5. Operating Modes and Resource Mapping 5.1 5.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.3.1 Normal Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.3.1.1 Normal Expanded Wide Mode . . . . . . . . . . . . . . . . . . . . .81 5.3.1.2 Normal Expanded Narrow Mode . . . . . . . . . . . . . . . . . . .81 5.3.1.3 Normal Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . .81 5.3.2 Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.3.2.1 Special Expanded Wide Mode . . . . . . . . . . . . . . . . . . . . .82 5.3.2.2 Special Expanded Narrow Mode . . . . . . . . . . . . . . . . . . .82 5.3.2.3 Special Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . .82 5.3.2.4 Special Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . .82 5.3.3 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.4 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.5 Mode and Resource Mapping Registers . . . . . . . . . . . . . . . . .85 5.5.1 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.5.2 Register Initialization Register . . . . . . . . . . . . . . . . . . . . . . .87 5.5.3 RAM Initialization Register . . . . . . . . . . . . . . . . . . . . . . . . . .88 5.5.4 EEPROM Initialization Register . . . . . . . . . . . . . . . . . . . . . .88 5.5.5 Miscellaneous Mapping Control Register . . . . . . . . . . . . . . .89 5.6 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Section 6. Bus Control and Input/Output (I/O) 6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Detecting Access Type from External Signals . . . . . . . . . . . . .94 6.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 6.4.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 6.4.2 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .96 6.4.3 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 6.4.4 Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .97 6.4.5 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 6.4.6 Port C Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .99 Advance Information MOTOROLA Table of Contents MC68HC812A4 -- Rev. 3.0 7 Table of Contents 6.4.7 6.4.8 6.4.9 6.4.10 6.4.11 6.4.12 6.4.13 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . .101 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Port E Data Direction Register . . . . . . . . . . . . . . . . . . . . . .103 Port E Assignment Register . . . . . . . . . . . . . . . . . . . . . . . .104 Pullup Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Section 7. EEPROM 7.1 7.2 7.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 EEPROM Programmer's Model . . . . . . . . . . . . . . . . . . . . . . .112 7.4 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .114 7.4.1 EEPROM Module Configuration Register . . . . . . . . . . . . .114 7.4.2 EEPROM Block Protect Register . . . . . . . . . . . . . . . . . . . .115 7.4.3 EEPROM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.4.4 EEPROM Programming Register . . . . . . . . . . . . . . . . . . . .117 Section 8. Memory Expansion and Chip-Select 8.1 8.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 8.3 Generation of Chip-Selects. . . . . . . . . . . . . . . . . . . . . . . . . . .124 8.3.1 Chip-Selects Independent of Memory Expansion . . . . . . .124 8.3.2 Chip-Selects Used in Conjunction with Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . .126 8.4 Chip-Select Stretch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 8.5 Memory Expansion Registers. . . . . . . . . . . . . . . . . . . . . . . . .130 8.5.1 Port F Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 8.5.2 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 8.5.3 Port F Data Direction Register . . . . . . . . . . . . . . . . . . . . . .131 8.5.4 Port G Data Direction Register . . . . . . . . . . . . . . . . . . . . . .131 8.5.5 Data Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 8.5.6 Program Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . .132 MC68HC812A4 -- Rev. 3.0 8 Table of Contents Advance Information MOTOROLA Table of Contents 8.5.7 8.5.8 8.5.9 8.6 Extra Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Window Definition Register . . . . . . . . . . . . . . . . . . . . . . . .133 Memory Expansion Assignment Register . . . . . . . . . . . . .134 Chip-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.7 Chip-Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 8.7.1 Chip-Select Control Register 0 . . . . . . . . . . . . . . . . . . . . . .136 8.7.2 Chip-Select Control Register 1 . . . . . . . . . . . . . . . . . . . . . .138 8.7.3 Chip-Select Stretch Registers . . . . . . . . . . . . . . . . . . . . . .139 8.8 Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Section 9. Key Wakeups 9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.3 Key Wakeup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.3.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.3.2 Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . .145 9.3.3 Port D Key Wakeup Interrupt Enable Register . . . . . . . . . .145 9.3.4 Port D Key Wakeup Flag Register . . . . . . . . . . . . . . . . . . .146 9.3.5 Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.3.6 Port H Data Direction Register . . . . . . . . . . . . . . . . . . . . . .147 9.3.7 Port H Key Wakeup Interrupt Enable Register . . . . . . . . . .147 9.3.8 Port H Key Wakeup Flag Register . . . . . . . . . . . . . . . . . . .148 9.3.9 Port J Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.3.10 Port J Data Direction Register . . . . . . . . . . . . . . . . . . . . . .149 9.3.11 Port J Key Wakeup Interrupt Enable Register . . . . . . . . . .149 9.3.12 Port J Key Wakeup Flag Register . . . . . . . . . . . . . . . . . . .150 9.3.13 Port J Key Wakeup Polarity Register . . . . . . . . . . . . . . . . .150 9.3.14 Port J Pullup/Pulldown Select Register . . . . . . . . . . . . . . .151 9.3.15 Port J Pullup/Pulldown Enable Register. . . . . . . . . . . . . . .152 Advance Information MOTOROLA Table of Contents MC68HC812A4 -- Rev. 3.0 9 Table of Contents Section 10. Clock Module 10.1 10.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 10.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 10.3.1 Clock Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 10.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 10.5.1 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . .156 10.5.2 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10.5.3 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10.5.4 Peripheral Clock Divider Chains. . . . . . . . . . . . . . . . . . . . .158 10.6 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .161 10.6.1 Real-Time Interrupt Control Register . . . . . . . . . . . . . . . . .161 10.6.2 Real-Time Interrupt Flag Register . . . . . . . . . . . . . . . . . . .163 10.6.3 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.6.4 Arm/Reset COP Timer Register . . . . . . . . . . . . . . . . . . . . .166 Section 11. Phase-Lock Loop (PLL) 11.1 11.2 11.3 11.4 11.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.6 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .171 11.6.1 Loop Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.6.2 Reference Divider Registers . . . . . . . . . . . . . . . . . . . . . . .172 11.6.3 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 MC68HC812A4 -- Rev. 3.0 10 Table of Contents Advance Information MOTOROLA Table of Contents Section 12. Standard Timer Module 12.1 12.2 12.3 12.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.5.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 12.5.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 12.5.4.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .185 12.5.4.2 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . .185 12.6 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .186 12.6.1 Timer IC/OC Select Register . . . . . . . . . . . . . . . . . . . . . . .186 12.6.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . .187 12.6.3 Timer Output Compare 7 Mask Register . . . . . . . . . . . . . .187 12.6.4 Timer Output Compare 7 Data Register. . . . . . . . . . . . . . .188 12.6.5 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . .189 12.6.6 Timer System Control Register . . . . . . . . . . . . . . . . . . . . .190 12.6.7 Timer Control Registers 1 and 2 . . . . . . . . . . . . . . . . . . . .192 12.6.8 Timer Control Registers 3 and 4 . . . . . . . . . . . . . . . . . . . .193 12.6.9 Timer Mask Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 12.6.10 Timer Mask Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 12.6.11 Timer Flag Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 12.6.12 Timer Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 12.6.13 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .197 12.6.14 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . .198 12.6.15 Pulse Accumulator Flag Register . . . . . . . . . . . . . . . . . . . .200 12.6.16 Pulse Accumulator Counter Registers . . . . . . . . . . . . . . . .201 12.6.17 Timer Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 12.7 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 12.7.1 Input Capture/Output Compare Pins . . . . . . . . . . . . . . . . .203 12.7.2 Pulse Accumulator Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 12.8 12.9 Advance Information MOTOROLA Table of Contents Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 MC68HC812A4 -- Rev. 3.0 11 Table of Contents 12.9.1 12.9.2 12.9.3 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.10 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.11 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.11.1 Timer Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.11.2 Timer Port Data Direction Register . . . . . . . . . . . . . . . . . .207 12.11.3 Data Direction Register for Timer Port . . . . . . . . . . . . . . . .208 12.12 Using the Output Compare Function to Generate a Square Wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 12.12.1 Sample Calculation to Obtain Period Counts . . . . . . . . . . .209 12.12.2 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12.12.3 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 Section 13. Multiple Serial Interface (MSI) 13.1 13.2 13.3 13.4 13.5 13.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 SCI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 SPI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 MSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 MSI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 13.7 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .218 13.7.1 Port S Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 13.7.2 Port S Data Direction Register . . . . . . . . . . . . . . . . . . . . . .220 13.7.3 Port S Pullup and Reduced Drive Control . . . . . . . . . . . . .221 13.7.4 Port S Wired-OR Mode Control . . . . . . . . . . . . . . . . . . . . .222 MC68HC812A4 -- Rev. 3.0 12 Table of Contents Advance Information MOTOROLA Table of Contents Section 14. Serial Communications Interface Module (SCI) 14.1 14.2 14.3 14.4 14.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 14.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 14.6.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 14.6.2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 14.6.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.6.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6.3.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6.3.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 14.6.3.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 14.6.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 14.6.4.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 14.6.4.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .237 14.6.4.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 14.6.4.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 14.6.4.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .243 14.6.4.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 14.6.5 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 14.6.6 Loop Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 14.7 Register Descriptions and Reset Initialization . . . . . . . . . . . .248 14.7.1 SCI Baud Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . .249 14.7.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 14.7.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 14.7.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 14.7.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 14.7.6 SCI Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 14.8 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14.8.1 TXD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14.8.2 RXD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Advance Information MOTOROLA Table of Contents MC68HC812A4 -- Rev. 3.0 13 Table of Contents 14.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.11 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 14.12 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .260 14.13 Serial Character Transmission using the SCI. . . . . . . . . . . . .260 14.13.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 14.13.2 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 Section 15. Serial Peripheral Interface (SPI) 15.1 15.2 15.3 15.4 15.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 15.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 15.6.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 15.6.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 15.6.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 15.6.4 Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . .268 15.6.5 SS Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 15.6.6 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 15.7 SPI Register Descriptions and Reset Initialization . . . . . . . . .273 15.7.1 SPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 15.7.2 SPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 15.7.3 SPI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . .276 15.7.4 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 15.7.5 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 15.8 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 15.8.1 MISO (Master In, Slave Out) . . . . . . . . . . . . . . . . . . . . . . .279 15.8.2 MOSI (Master Out, Slave In) . . . . . . . . . . . . . . . . . . . . . . .279 MC68HC812A4 -- Rev. 3.0 14 Table of Contents Advance Information MOTOROLA Table of Contents 15.8.3 15.8.4 SCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 15.10 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 15.11 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .281 15.12 Synchronous Character Transmission using the SPI . . . . . . .282 15.12.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 15.12.2 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Section 16. Analog-to-Digital Converter (ATD) 16.1 16.2 16.3 16.4 16.5 16.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 16.7 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .291 16.7.1 ATD Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .291 16.7.2 ATD Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .291 16.7.3 ATD Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .292 16.7.4 ADT Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .293 16.7.5 ATD Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . .294 16.7.6 ATD Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . .296 16.7.7 ATD Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 16.7.8 ATD Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.7.9 ATD Result Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 16.8 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 16.8.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 16.8.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 16.8.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 Advance Information MOTOROLA Table of Contents MC68HC812A4 -- Rev. 3.0 15 Table of Contents 16.9 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 16.10 General-Purpose Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 16.11 Port AD Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 16.12 Using the ATD to Measure a Potentiometer Signal . . . . . . . .303 16.12.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 16.12.2 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 Section 17. Development Support 17.1 17.2 17.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 17.4 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . .307 17.4.1 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 17.4.2 Enabling BDM Firmware Commands . . . . . . . . . . . . . . . . .311 17.4.3 BDM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 17.5 BDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.5.1 BDM Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.5.1.1 Hardware Command . . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.5.1.2 Firmware Command. . . . . . . . . . . . . . . . . . . . . . . . . . . .315 17.5.2 BDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 17.5.3 BDM Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 17.5.4 BDM Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .318 17.5.5 BDM CCR Holding Register . . . . . . . . . . . . . . . . . . . . . . . .319 17.6 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 Section 18. Electrical Characteristics 18.1 18.2 18.3 18.4 18.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .323 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .324 MC68HC812A4 -- Rev. 3.0 16 Table of Contents Advance Information MOTOROLA Table of Contents 18.6 18.7 18.8 18.9 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 ATD Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 ATD DC Electrical Characteristcs. . . . . . . . . . . . . . . . . . . . . .326 Analog Converter Operating Characteristics . . . . . . . . . . . . .327 18.10 ATD AC Operating Characteristics . . . . . . . . . . . . . . . . . . . . .328 18.11 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 18.12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 18.13 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 18.14 Non-Multiplexed Expansion Bus Timing . . . . . . . . . . . . . . . . .334 18.15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 Section 19. Mechanical Specifications 19.1 19.2 19.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 112-Pin Low-Profile Quad Flat Pack (Case 987) . . . . . . . . . .340 Advance Information MOTOROLA Table of Contents MC68HC812A4 -- Rev. 3.0 17 Table of Contents MC68HC812A4 -- Rev. 3.0 18 Table of Contents Advance Information MOTOROLA Advance Information -- MC68HC812A4 List of Figures Figure 1-1 1-2 1-3 1-4 Title Page Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Expanded Wide Mode FLASH EEPROM Expansion Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Expanded Narrow Mode FLASH EEPROM Expansion Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Accumulator A (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Accumulator B (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Accumulator D (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Index Register X (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Index Register Y (Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .63 Interrupt Control Register (INTCR) . . . . . . . . . . . . . . . . . . . . . .73 Highest Priority I Interrupt Register (HPRIO) . . . . . . . . . . . . . .74 Mode Register (MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Register Initialization Register (INITRG). . . . . . . . . . . . . . . . . .87 RAM Initialization Register (INITRM) . . . . . . . . . . . . . . . . . . . .88 EEPROM Initialization Register (INITEE) . . . . . . . . . . . . . . . . .89 Miscellaneous Mapping Control Register (MISC). . . . . . . . . . .90 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 Advance Information MOTOROLA List of Figures MC68HC812A4 -- Rev. 3.0 19 List of Figures Figure 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 Title Page Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . .96 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . .96 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . .97 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . .97 Port C Data Register (PORTC). . . . . . . . . . . . . . . . . . . . . . . . .98 Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . . . .99 Port D Data Register (PORTD). . . . . . . . . . . . . . . . . . . . . . . .100 Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . .101 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . .102 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . .103 Port E Assignment Register (PEAR) . . . . . . . . . . . . . . . . . . .104 Pullup Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . .107 Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . .108 EEPROM Block Protect Mapping . . . . . . . . . . . . . . . . . . . . . .113 EEPROM Module Configuration Register (EEMCR) . . . . . . .114 EEPROM Block Protect Register (EEPROT) . . . . . . . . . . . . .115 EEPROM Test Register (EEPROT) . . . . . . . . . . . . . . . . . . . .116 EEPROM Programming Register (EEPROG) . . . . . . . . . . . .117 Chip-Selects CS3-CS0 Partial Memory Map . . . . . . . . . . . . .125 Memory Expansion and Chip-Select Example . . . . . . . . . . . .127 Chip-Select with No Stretch . . . . . . . . . . . . . . . . . . . . . . . . . .128 Chip-Select with One-Cycle Stretch . . . . . . . . . . . . . . . . . . . .128 Chip-Select with 2-Cycle Stretch . . . . . . . . . . . . . . . . . . . . . .129 Chip-Select with 3-Cycle Stretch . . . . . . . . . . . . . . . . . . . . . .129 Port F Data Register (PORTF) . . . . . . . . . . . . . . . . . . . . . . . .130 Port G Data Register (PORTG) . . . . . . . . . . . . . . . . . . . . . . .130 Port F Data Direction Register (DDRF) . . . . . . . . . . . . . . . . .131 Port G Data Direction Register (DDRG) . . . . . . . . . . . . . . . . .131 Data Page Register (DPAGE) . . . . . . . . . . . . . . . . . . . . . . . .132 Program Page Register (PPAGE) . . . . . . . . . . . . . . . . . . . . .132 Extra Page Register (EPAGE) . . . . . . . . . . . . . . . . . . . . . . . .133 Window Definition Register (WINDEF) . . . . . . . . . . . . . . . . . .133 Memory Expansion Assignment Register (MXAR) . . . . . . . . .134 MC68HC812A4 -- Rev. 3.0 20 List of Figures Advance Information MOTOROLA List of Figures Figure 8-16 8-17 8-18 8-19 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 Title Page . . . . . . . . . . . . . . .136 . . . . . . . . . . . . . . .138 . . . . . . . . . . . . . . .139 . . . . . . . . . . . . . . .139 Chip-Select Control Register 0 (CSCTL0) Chip-Select Control Register 1 (CSCTL1) Chip-Select Stretch Register 0 (CSSTR0) Chip-Select Stretch Register 1 (CSSTR1) Port D Data Register (PORTD). . . . . . . . . . . . . . . . . . . . . . . .144 Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . .145 Port D Key Wakeup Interrupt Enable Register (KWIED) . . . .145 Port D Key Wakeup Flag Register (KWIFD). . . . . . . . . . . . . .146 Port H Data Register (PORTH). . . . . . . . . . . . . . . . . . . . . . . .146 Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . .147 Port H Key Wakeup Interrupt Enable Register (KWIEH) . . . .147 Port H Key Wakeup Flag Register (KWIFH). . . . . . . . . . . . . .148 Port J Data Register (PORTJ) . . . . . . . . . . . . . . . . . . . . . . . .148 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . .149 Port J Key Wakeup Interrupt Enable Register (KWIEJ) . . . . .149 Port J Key Wakeup Flag Register (KWIFJ) . . . . . . . . . . . . . .150 Port J Key Wakeup Polarity Register (KPOLJ). . . . . . . . . . . .150 Port J Pullup/Pulldown Select Register (PUPSJ) . . . . . . . . . .151 Port J Pullup/Pulldown Enable Register (PULEJ). . . . . . . . . .152 Clock Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .154 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .155 Clock Function Register Map . . . . . . . . . . . . . . . . . . . . . . . . .156 Clock Chain for SCI0, SCI1, RTI, and COP . . . . . . . . . . . . . .158 Clock Chain for TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Clock Chain for SPI, ATD and BDM . . . . . . . . . . . . . . . . . . . .160 Real-Time Interrupt Control Register (RTICTL) . . . . . . . . . . .161 Real-Time Interrupt Flag Register (RTIFLG) . . . . . . . . . . . . .163 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .163 Arm/Reset COP Timer Register (COPRST) . . . . . . . . . . . . . .166 11-1 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11-2 PLL Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11-3 Loop Divider Register High (LDVH) . . . . . . . . . . . . . . . . . . . .171 Advance Information MOTOROLA List of Figures MC68HC812A4 -- Rev. 3.0 21 List of Figures Figure 11-4 11-5 11-6 11-7 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 12-26 12-27 12-28 Title Page Loop Divider Register Low (LDVL) . . . . . . . . . . . . . . . . . . . . .171 Reference Divider Register High (RDVH). . . . . . . . . . . . . . . .172 Reference Divider Register Low (RDVL) . . . . . . . . . . . . . . . .172 Clock Control Register (CLKCTL). . . . . . . . . . . . . . . . . . . . . .173 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Channel 7 Output Compare/Pulse Accumulator Logic . . . . . .186 Timer IC/OC Select Register (TIOS) . . . . . . . . . . . . . . . . . . .186 Timer Compare Force Register (CFORC) . . . . . . . . . . . . . . .187 Timer Output Compare 7 Mask Register (OC7M) . . . . . . . . .187 Timer Output Compare 7 Data Register (OC7D) . . . . . . . . . .188 Timer Counter Register High (TCNTH) . . . . . . . . . . . . . . . . .189 Timer Counter Register Low (TCNTL) . . . . . . . . . . . . . . . . . .189 Timer System Control Register (TSCR) . . . . . . . . . . . . . . . . .190 Fast Clear Flag Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 Timer Control Register 1 (TCTL1) . . . . . . . . . . . . . . . . . . . . .192 Timer Control Register 2 (TCTL2) . . . . . . . . . . . . . . . . . . . . .192 Timer Control Register 3 (TCTL3) . . . . . . . . . . . . . . . . . . . . .193 Timer Control Register 4 (TCTL4) . . . . . . . . . . . . . . . . . . . . .193 Timer Mask 1 Register (TMSK1) . . . . . . . . . . . . . . . . . . . . . .194 Timer Mask 2 Register (TMSK2) . . . . . . . . . . . . . . . . . . . . . .194 Timer Flag Register 1 (TFLG1). . . . . . . . . . . . . . . . . . . . . . . .196 Timer Flag Register 2 (TFLG2). . . . . . . . . . . . . . . . . . . . . . . .196 Timer Channel Registers (TCxH/L) . . . . . . . . . . . . . . . . . . . .197 Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . .198 Pulse Accumulator Flag Register (PAFLG) . . . . . . . . . . . . . .200 Pulse Accumulator Counter Registers (PACNTH/L). . . . . . . .201 Timer Test Register (TIMTST) . . . . . . . . . . . . . . . . . . . . . . . .202 Timer Port Data Register (PORTT) . . . . . . . . . . . . . . . . . . . .206 Timer Port Data Direction Register (DDRT) . . . . . . . . . . . . . .207 Data Direction Register for Timer Port (DDRT) . . . . . . . . . . .208 Example Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 MC68HC812A4 -- Rev. 3.0 22 List of Figures Advance Information MOTOROLA List of Figures Figure 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24 15-1 15-2 15-3 15-4 15-5 Advance Information MOTOROLA List of Figures Title Page Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .215 MSI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 Port S Data Register (PORTS) . . . . . . . . . . . . . . . . . . . . . . . .219 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . .220 SPI Control Register 2 (SP0CR2). . . . . . . . . . . . . . . . . . . . . .221 SCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 SCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 SCI Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . .232 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .236 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 Start Bit Search Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . .240 Start Bit Search Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . .240 Start Bit Search Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . .241 Start Bit Search Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . .241 Start Bit Search Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . .242 Start Bit Search Example 6. . . . . . . . . . . . . . . . . . . . . . . . . . .242 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 Single-Wire Operation (LOOPS = 1 and RSRC = 1) . . . . . . .247 Loop Operation (LOOP = 1 and RSRC = 0) . . . . . . . . . . . . . .248 SCI Baud Rate Register High (SC0BDH or SC1BDH) . . . . . .249 SCI Baud Rate Register Low (SC0BDL or SC1BDL) . . . . . . .249 SCI Control Register 1 (SC0CR1 or SC1CR1). . . . . . . . . . . .250 SCI Control Register 2 (SC0CR2 or SC1CR2). . . . . . . . . . . .252 SCI Status Register 1 (SC0SR1 or SC1SR1). . . . . . . . . . . . .254 SCI Status Register 2 (SC0SR2 or SC1SR2). . . . . . . . . . . . .256 SCI Data Register High (SC0DRH or SC1DRH) . . . . . . . . . .257 SCI Data Register Low (SC0DRL or SC1DRL) . . . . . . . . . . .257 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 SPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 Full-Duplex Master/Slave Connections. . . . . . . . . . . . . . . . . .267 Transmission Format 0 (CPHA = 0) . . . . . . . . . . . . . . . . . . . .269 Slave SS Toggling When CPHA = 0. . . . . . . . . . . . . . . . . . . .269 MC68HC812A4 -- Rev. 3.0 23 List of Figures Figure 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 Title Page Transmission Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . .270 Slave SS When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .270 Single-Wire Operation (SPC0 = 1) . . . . . . . . . . . . . . . . . . . . .272 SPI Control Register 1 (SP0CR1). . . . . . . . . . . . . . . . . . . . . .273 SPI Control Register 2 (SP0CR2). . . . . . . . . . . . . . . . . . . . . .275 SPI Baud Rate Register (SP0BR) . . . . . . . . . . . . . . . . . . . . .276 SPI Status Register (SP0SR) . . . . . . . . . . . . . . . . . . . . . . . . .277 SPI Data Register (SP0DR) . . . . . . . . . . . . . . . . . . . . . . . . . .278 ATD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 ATD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .288 ATD Control Register 0 (ATDCTL0) . . . . . . . . . . . . . . . . . . . .291 ATD Control Register 1 (ATDCTL1) . . . . . . . . . . . . . . . . . . . .291 ATD Control Register 2 (ATDCTL2) . . . . . . . . . . . . . . . . . . . .292 ATD Control Register 3 (ATDCTL3) . . . . . . . . . . . . . . . . . . . .293 ATD Control Register 4 (ATDCTL4) . . . . . . . . . . . . . . . . . . . .294 ATD Control Register 5 (ATDCTL5) . . . . . . . . . . . . . . . . . . . .296 ATD Status Register 1 (ATDSTAT1) . . . . . . . . . . . . . . . . . . .298 ATD Status Register 2 (ATDSTAT2) . . . . . . . . . . . . . . . . . . .298 ATD Test Register 1 (ATDTEST1) . . . . . . . . . . . . . . . . . . . . .299 ATD Test Register 2 (ATDTEST2) . . . . . . . . . . . . . . . . . . . . .299 ATD Result Registers (ADR0H-ADR7H) . . . . . . . . . . . . . . . .300 Port AD Data Input Register (PORTAD). . . . . . . . . . . . . . . . .302 BDM Host-to-Target Serial Bit Timing . . . . . . . . . . . . . . . . . .309 BDM Target-to-Host Serial Bit Timing (Logic 1) . . . . . . . . . . .310 BDM Target-to-Host Serial Bit Timing (Logic 0) . . . . . . . . . . .310 BDM Instruction Register (INSTRUCTION) . . . . . . . . . . . . . .314 BDM Instruction Register (INSTRUCTION) . . . . . . . . . . . . . .315 BDM Status Register (STATUS). . . . . . . . . . . . . . . . . . . . . . .317 BDM Shift Register (SHIFTER) . . . . . . . . . . . . . . . . . . . . . . .318 BDM Address Register (ADDRESS) . . . . . . . . . . . . . . . . . . .318 BDM CCR Holding Register (CCRSAV) . . . . . . . . . . . . . . . . .319 MC68HC812A4 -- Rev. 3.0 24 List of Figures Advance Information MOTOROLA List of Figures Figure 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 Title Page Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .330 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .331 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .332 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .333 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .333 Non-Multiplexed Expansion Bus Timing Diagram . . . . . . . . .335 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 Advance Information MOTOROLA List of Figures MC68HC812A4 -- Rev. 3.0 25 List of Figures MC68HC812A4 -- Rev. 3.0 26 List of Figures Advance Information MOTOROLA Advance Information -- MC68HC812A4 List of Tables Table 1-1 1-2 1-3 1-4 3-1 3-2 4-1 4-2 5-1 5-2 6-1 7-1 7-2 8-1 8-2 8-3 8-4 8-5 Title Page Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Port Pullup, Pulldown, and Reduced Drive Summary . . . . . . .37 Addressing Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . .65 Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .66 Interrupt Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . . .78 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Access Type versus Bus Control Pins . . . . . . . . . . . . . . . . . . .94 4-Kbyte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .115 Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Memory Expansion Values . . . . . . . . . . . . . . . . . . . . . . . . . .123 Example Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . .125 Example Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Module Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 10-1 Clock Monitor Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10-2 Real-Time Interrupt Rates . . . . . . . . . . . . . . . . . . . . . . . . . . .162 10-3 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 11-1 PLL Filter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 11-2 Base Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Advance Information MOTOROLA List of Tables MC68HC812A4 -- Rev. 3.0 27 List of Tables Table Title Page 11-3 Module Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 12-1 12-2 12-3 12-4 12-5 12-6 Selection of Output Compare Action . . . . . . . . . . . . . . . . . . .192 Input Capture Edge Selection. . . . . . . . . . . . . . . . . . . . . . . . .193 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Timer Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 TIMPORT I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 13-1 Port S Pullup and Reduced Drive Enable. . . . . . . . . . . . . . . .221 13-2 Port S Wired-OR Mode Enable. . . . . . . . . . . . . . . . . . . . . . . .222 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 15-1 15-2 15-3 15-4 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 17-5 Example 8-Bit Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . .229 Example 9-Bit Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . .230 Baud Rates (Module Clock = 10.2 MHz) . . . . . . . . . . . . . . . .231 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Loop Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 SCI Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 SS Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 SPI Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 ATD Response to Background Debug Enable . . . . . . . . . . . .294 Final Sample Time Selection . . . . . . . . . . . . . . . . . . . . . . . . .294 Clock Prescaler Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 Multichannel Mode Result Register Assignment . . . . . . . . . .297 SPI Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 IPIPE Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 BDM Commands Implemented in Hardware . . . . . . . . . . . . .312 BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . .313 TTAGO Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 REGN Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 MC68HC812A4 -- Rev. 3.0 28 List of Tables Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 1. General Description 1.1 Contents 1.2 1.3 1.4 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.2 Introduction The MC68HC812A4 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include: * * * * * * * * * 16-bit central processor unit (CPU12) Lite integration module (LIM) Two asynchronous serial communications interfaces (SCI0 and SCI1) Serial peripheral interface (SPI) Timer and pulse accumulator module 8-bit analog-to-digital converter (ATD) 1-Kbyte random-access memory (RAM) 4-Kbyte electrically erasable, programmable read-only memory (EEPROM) Memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop (PLL) Advance Information MOTOROLA General Description MC68HC812A4 -- Rev. 3.0 29 General Description 1.3 Features Features of the MC68HC812A4 include: * * * Low-power, high-speed M68HC12 CPU Power-saving stop and wait modes Memory - 1024-byte RAM - 4096-byte EEPROM - On-chip memory mapping allows expansion to more than 5-Mbyte address space * * * * Single-wire Background Debug(R) mode Non-multiplexed address and data buses Seven programmable chip-selects with clock stretching (expanded modes) 8-channel, enhanced 16-bit timer with programmable prescaler - All channels configurable as input capture or output compare - Flexible choice of clock source * * * * * * * * * * 16-bit pulse accumulator Real-time interrupt circuit Computer operating properly (COP) watchdog Clock monitor Phase-locked loop (PLL) Two enhanced asynchronous non-return-to-zero (NRZ) serial communication interfaces (SCI) Enhanced synchronous serial peripheral interface (SPI) 8-channel, 8-bit analog-to-digital converter (ATD) Up to 24 key wakeup lines with interrupt capability Available in 112-lead low-profile quad flat pack (LQFP) packaging (R) Background Debug is a registered trademark of Motorola, Inc. MC68HC812A4 -- Rev. 3.0 30 General Description Advance Information MOTOROLA General Description Ordering Information 1.4 Ordering Information The MC68HC812A4 is available in 112-lead low-profile quad flat pack (LQFP) packaging. Operating temperature range and voltage requirements are specified when ordering the MC68HC812A4 device. Refer to Table 1-1 for part numbers. Table 1-1. Ordering Information Temperature Order Number Range MC68HC812A4PV 0 to +70 C Designator -- 3.3 Voltage Frequency (MHz) 2.0 Evaluation boards, assemblers, compilers, and debuggers are available from Motorola and from third-party suppliers. An up-to-date list of products that support the M68HC12 Family of microcontrollers can be found on the worldwide web at this URL: http://www.mcu.motsps.com Documents to assist in product selection are available from the Motorola Literature Distribution Center or local Motorola sales offices. Advance Information MOTOROLA General Description MC68HC812A4 -- Rev. 3.0 31 General Description 1.5 Block Diagram 1-KBYTE SRAM VRH VRL VDDA VSSA VSTBY/AN7 AN6 AN5 A/D CONVERTER AN4 AN3 AN2 AN1 AN0 LMB - LITE MODULE BUS IOC7/PAI IOC6 IOC5 IOC4 OC7 IOC3 IOC2 IOC1 IOC0 VRH VRL VDDA VSSA PAD7VSTBY PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 4-KBYTE EEPROM CPU12 BKGD/TAGHI RESET EXTAL XTAL XFC VDDPLL VSSPLL PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 SINGLE-WIRE BACKGROUND DEBUG MODULE PLL CLOCK CONTROL ARST IPIPE1/MODB IPIPE0/MODA ECLK LSTRB/TAGLO R/W IRQ/VPP XIRQ KWJ7 KWJ6 KWJ5 KWJ4 KWJ3 KWJ2 KWJ1 KWJ0 KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7/KWD7 DATA6/KWD6 DATA5/KWD5 DATA4/KWD4 DATA3/KWD3 DATA2/KWD2 DATA1/KWD1 DATA0/KWD0 PERIODIC INTERRUPT COP WATCHDOG CLOCK MONITOR INTERRUPT BLOCK PORT AD DDRS PORT S / PU PORT T / PU DDRT TIM PORT E / PU DDRE PORT J / PU / PD SS SCK SDO/MOSI SDI/MISO MSI TXD1 SCI1 RXD1 TXD0 SCI0 RXD0 SPI0 CSP1 CSP0 CSD CS3 CS2 CS1 CS0 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PG5 PG4 PG3 PG2 PG1 PG0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DDRJ LIM LITE INTEGRATION MODULE PORT H / PU PORT G / PU DDRH DDRG PORT F / PU DDRF PORT C / PU PORT A / PU VDDEXT x3 VSSEXT x3 DDRC DDRA VDD x1 VSSI x1 PORT D / PU NON-MULTIPLEXED ADDRESS/DATA BUS Figure 1-1. Block Diagram MC68HC812A4 -- Rev. 3.0 32 General Description Advance Information MOTOROLA PORT B / PU DDRD DDRB General Description Signal Descriptions 1.6 Signal Descriptions NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. The MC68HC812A4 is available in a 112-lead low-profile quad flat pack (LQFP). The pin assignments are shown in Figure 1-2. Most pins perform two or more functions, as described in Table 1-2. Individual ports are cross referenced in Table 1-3 and Table 1-4. PH7/KWH7 PH6/KWH6 PH5/KWH5 PH4/KWH4 VSSX VDDX PH3/KWH3 PH2/KWH2 PH1/KWH1 PH0/KWH0 PF6/CSP1 PF5/CSP0 PF4/CSD PF3/CS3 PF2/CS2 PF1/CS1 PF0/CS0 PA7/ADDR15 PA6/ADDR14 PA5/ADDR13 PA4/ADDR12 PA3/ADDR11 PA2/ADDR10 PA1/ADDR9 PA0/ADDR8 PB7/ADDR7 PB6/ADDR6 PB5/ADDR5 VRH VRL PAD0/AN0 PAD1/AN1 PAD2/AN2 PAD3/AN3 PAD4/AN4 PAD5/AN5 PAD6/AN6 PAD7/AN7/VSTBY VDDA VSSA PS0/RxD0 PS1/TxD0 PS2/RxD1 PS3/TxD1 PS4/SDI/MISO PS5/SDO/MOSI PS6/SCK PS7/SS PT0/IOC0 PT1/IOC1 PT2/IOC2 PT3/IOC3 PT4/IOC4 PT5/IOC5 PT6/IOC6 PT7/IOC7/PAI 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 MC68HC812A4 112-LEAD LQFP 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ADDR4/PB4 ADDR3/PB3 ADDR2/PB2 ADDR1/PB1 ADDR0/PB0 ARST/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 XTAL EXTAL VSSPLL XFC VDDPLL VDDX VSSX RESET LSTRB/TAGLO/PE3 R/W/PE2 IRQ/VPP/PE1 XIRQ/PE0 DATA15/PC7 DATA14/PC6 DATA13/PC5 DATA12/PC4 DATA11/PC3 DATA10/PC2 DATA9/PC1 Advance Information MOTOROLA General Description VSSX VDDX KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3 KWJ4/PJ4 KWJ5/PJ5 KWJ6/PJ6 KWJ7/PJ7 ADDR16/PG0 ADDR17/PG1 ADDR18/PG2 VDD VSS ADDR19/PG3 ADDR20/PG4 ADDR21/PG5 BKGD / TAGHI DATA0/KWD0/PD0 DATA1/KWD1/PD1 DATA2/KWD2/PD2 DATA3/KWD3/PD3 DATA4/KWD4/PD4 DATA5/KWD5/PD5 DATA6/KWD6/PD6 DATA7/KWD7/PD7 DATA8/PC0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 1-2. Pin Assignments MC68HC812A4 -- Rev. 3.0 33 General Description Table 1-2. Pin Descriptions Pin VDD, VSS VRH, VRL AVDD, AVSS VDDPLL, VSSPLL VSTBY XTAL, EXTAL XIRQ IRQ R/W LSTRB ECLK BKGD MODA MODB IPIPE0 IPIPE1 ARST XFC RESET ADDR15-ADDR8 ADDR7-ADDR0 DATA15-DATA8 DATA7-DATA0 Port -- -- -- -- Description Operating voltage and ground for the MCU(1) Reference voltages for the ADC Operating voltage and ground for the ADC(2) Power and ground for PLL clock control Port AD RAM standby power input -- PE0 PE1 PE2 PE3 PE4 -- PE5 PE6 PE5 Instruction queue tracking signals for development systems PE6 PE7 -- -- Port A Port B Single-chip modes: general-purpose I/O Expanded modes: external bus pins Port C Port D in narrow data bus mode: general-purpose I/O or key wakeup port Port D Alternate active-high reset input General-purpose I/O Loop filter pin for controlled damping of PLL VCO loop Active-low bidirectional control signal; input initializes MCU to known startup state; output when COP or clock monitor causes a reset Input pins for either a crystal or a CMOS compatible clock(3) Asynchronous, non-maskable external interrupt request input Asynchronous, maskable external interrupt request input with selectable falling-edge triggering or low-level triggering Expansion bus data direction indicator General-purpose I/O; read/write in expanded modes Low byte strobe (0 = low byte valid)(4) General-purpose I/O Timing reference output for external bus clock (normally, half the crystal frequency) General-purpose I/O Mode-select pin determines initial operating mode of the MCU after reset Mode-select input determines initial operating mode of the MCU after reset(5) Mode-select input determines initial operating mode of the MCU after reset(5) MC68HC812A4 -- Rev. 3.0 34 General Description Advance Information MOTOROLA General Description Signal Descriptions Table 1-2. Pin Descriptions (Continued) Pin Port Description ADDR21-ADDR16 Port G Memory expansion and general-purpose I/O CS3-CS0,CSD, CSP1, CSP0 BKGD KWD7-KWD0 KWH7-KWH0 KWJ7-KWJ0 RxD0 TxD0 RxD1 TxD1 SDI/MISO SDO/MOSI SCK SS IOC7-IOC0 Port F -- Chip selects General-purpose I/O Single-wire background debug pin Mode-select pin that determines special or normal operating mode after reset Port D Key wakeup pins that can generate interrupt requests on high-to-low transitions Port H General-purpose I/O Port J PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 Key wakeup pins that can generate interrupt requests on any transition General-purpose I/O Receive pin for SCI0 Transmit pin for SCI0 Receive pin for SCI1 Transmit pin for SCI1 Master in/slave out pin for SPI Master out/slave in pin for SPI Serial clock for SPI Slave select output for SPI in master mode; slave select input in slave mode Port T Input capture or output compare channels and pulse accumulator input 1. The MCU operates from a single power supply. Use the customary bypass techniques as very fast signal transitions occur on MCU pins. 2. Separate power supply pins allow the ADC power supply to be bypassed independently of the MCU power supply. 3. Out of reset the frequency applied to EXTAL is twice the desired E-clock rate. On reset all device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 4. LSTRB is the exclusive-NOR of A0 and the internal SZ8 signal. SZ8 indicates the size 16/8 access. 5. After reset, MODA and MODB can be configured as instruction queue tracking signals IPIPE0 and IPIPE1 or as general-purpose I/O pins. Advance Information MOTOROLA General Description MC68HC812A4 -- Rev. 3.0 35 General Description Table 1-3. Port Descriptions Port Port A Port B Direction I/O I/O Function Single-chip modes: general-purpose I/O Expanded modes: external address bus ADDR15-ADDR8 Single-chip modes: general-purpose I/O Expanded modes: external address bus ADDR7-ADDR0 Single-chip modes: general-purpose I/O Expanded wide modes: external data bus DATA15-DATA8 Expanded narrow modes: external data bus DATA15-DATA8/DATA7-DATA0 Single-chip and expanded narrow modes: general-purpose I/O External data bus DATA7-DATA0 in expanded wide mode(1) External interrupt request inputs, mode select inputs, bus control signals General-purpose I/O Chip select General-purpose I/O Memory expansion General-purpose I/O Key wakeup(3) General-purpose I/O Key wakeup(4) General-purpose I/O SCI and SPI ports General-purpose I/O Timer port General-purpose I/O ADC port General-purpose input Port C I/O Port D Port E Port F Port G Port H I/O I/O and I(2) I/O I/O I/O Port J Port S Port T Port AD I/O I/O I/O I 1. Key wakeup interrupt request can occur when an input goes from high to low. 2. PE1 and PE0 are input-only pins. 3. Key wakeup interrupt request can occur when an input goes from high to low. 4. Key wakeup interrupt request can occur when an input goes from high to low or from low to high. MC68HC812A4 -- Rev. 3.0 36 General Description Advance Information MOTOROLA General Description Signal Descriptions Table 1-4. Port Pullup, Pulldown, and Reduced Drive Summary Enable Bit Port Name Port A Port B Port C Port D Port E: PE7, PE3, PE2, PE0 Port E: PE1 Port E: PE4 Port E: PE6 and PE5 Port F Port G Port H Port J Port S Port T Port AD BKGD Resistive Input Loads Pullup Pullup Pullup Pullup Pullup Register (Address) PUCR ($000C) PUCR ($000C) PUCR ($000C) PUCR ($000C) PUCR ($000C) Bit Name PUPA PUPB PUPC PUPD PUPE Reset State Enabled Enabled Enabled Enabled Enabled Reduced Drive Control Bit Register (Address) RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) Bit Name Reset State RDPAB Full drive RDPAB Full drive RDPC RDPD RDPE Full drive Full drive Full drive Pullup None Pulldown Pullup Pullup Pullup Pullup/down(1) Pullup Pullup None Pullup -- Always enabled -- Enabled during reset PUCR ($000C) PUCR ($000C) PUCR ($000C) PULEJ ($002E) SP0CR2 ($00D1) TMSK2 ($008D) -- -- Enabled PUPF PUPG PUPH Enabled Enabled Enabled RDRIV ($000D) RDRIV ($000D) -- RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) RDPE RDPE -- RDPF RDPG RDPH RDPJ RDS RDPT -- Full drive Full drive -- Full drive Full drive Full drive Full drive Full drive Full drive PULEJ[7:0] Disabled PUPS PUPT Enabled SP0CR2 ($00D1) Enabled TMSK2 ($008D) -- -- Full drive 1. Pullup or pulldown devices for each port J pin can be selected with the PUPSJ register ($002D). After reset, pulldowns are selected for all port J pins but must be enabled with PULEJ register. Advance Information MOTOROLA General Description MC68HC812A4 -- Rev. 3.0 37 General Description VDD VDD 4.7 k S1 1 2 SW DIP-2 4 3 PE5 PE6 PLL FILTER Y1 4.7 k VDD GROUND 14 15 42 79 1 41 44 43 45 40 47 46 36 37 38 39 48 49 50 51 19 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT[0..7] PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD[0..7] 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 3 4 5 6 7 8 9 10 87 88 89 90 91 92 93 94 VDD VSS VDDX0 VDDX1 VSSX0 VSSX1 XFC VDDPLL VSSPLL RESET XTAL EXTAL PE0/XIRQ PE1/IRQ PE2/R/W PE3/LSTRB PE4/ECLK PE5/MODA PE6/MODB PE7/ARST BKPD/TAGHI PS0/RxD0 PS1/RxD0 PS2/TxD1 PS3/TxD12 PS4/SDI/MISO PS5/SD0/MOSI PS6/SCK PS7/SS PT0/IOC0 PT1/IOC1 PT2/IOC2 PT3/IOC3 PT4/IOC4 PT5/IOC5 PT6/IOC6 PT7/IOC7 PJ0/KWJ0 PJ1/KWJ1 PJ2/KWJ2 PJ3/KWJ3 PJ5/KWJ4 PJ5/KWJ5 PJ6/KWJ6 PJ7/KWJ7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 U1 MC68HC812A4 PB0/ADDR00 PB1/ADDR01 PB2/ADDR02 PB3/ADDR03 PB4/ADDR04 PB5/ADDR05 PB6/ADDR06 PB7/ADDR07 PA0/ADDR08 PA1/ADDR09 PA2/ADDR10 PA3/ADDR11 PA4/ADDR12 PA5/ADDR13 PA6/ADDR14 PA7/ADDR15 PG0/ADDR16 PG1/ADDR17 PG2/ADDR18 PG3/ADDR19 PG4/ADDR20 PG5/ADDR21 PD0/KWD0/DATA0 PD1/KWD1/DATA1 PD2/KWD2/DATA2 PD3/KWD3/DATA3 PD4/KWD4/DATA4 PD5/KWD5/DATA5 PD6/KWD6/DATA6 PD7/KWD7/DATA7 PC0/DATA08 PC1/DATA09 PC2/DATA10 PC3/DATA11 PC4/DATA12 PC5/DATA13 PD6/DATA14 PC7/DATA15 PF0/CS0 PF1/CS1 PF2/CS2 PF3/CS3 PF4/CSD PF5/CSP0 PF6/CSP1 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 11 12 13 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 68 69 70 71 72 73 74 75 76 77 78 81 82 83 84 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF[0..7] PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH[0..7] A[0..21] R1 XFC R2 XTAL R3 EXTAL S1 A4_RESET PE[0..7] BKPTA JP2 1 2 3 4 5 6 C3 C4 RESETA PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 A0 A0 GROUND VDD HEADER 6 1 2 3 4 5 6 BKPTA D[0..15] PS[0..7] RESETA RSET MC34064 GND IN 2 3 1 U2 VCC PJ[0..7] C6 1.0 F C7 0.1 F C8 0.1 F C9 0.1 F Figure 1-3. Expanded Wide Mode FLASH EEPROM Expansion Schematic (Sheet 1 of 3) MC68HC812A4 -- Rev. 3.0 38 General Description Advance Information MOTOROLA General Description Signal Descriptions A[0. . 15] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 PE2 PF6 PE3 A0 5 4 3 2 1 44 43 42 27 26 25 24 21 20 19 18 17 16 4 39 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 WE CS BHE BLE U4 IDT71016 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D(0. . 15] VCC VSS 33 34 VCC PF[0. . 7] PE[0. . 7] Figure 1-3. Expanded Wide Mode FLASH EEPROM Expansion Schematic (Sheet 2 of 3) D(0. . 15] A(0. . 21] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 RESETA VCC 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 12 37 27 46 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 RESET VCC VSS VSS1 U3 AM29DL400B DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CE OE BYTE# WE RY/BY 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 26 28 47 11 15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PF5 PF[0. . 7] VCC_ARROW R5 RESISTOR S3 MODE_SELECT PE2 PE[0. . 7] Figure 1-3. Expanded Wide Mode FLASH EEPROM Expansion Schematic (Sheet 2 of 3) Advance Information MOTOROLA General Description MC68HC812A4 -- Rev. 3.0 39 General Description VDD VDD 4.7 k S1 1 2 SW DIP-2 4 3 PE5 PE6 PLL FILTER Y1 4.7 k VDD GROUND 14 15 42 79 1 41 44 43 45 40 47 46 36 37 38 39 48 49 50 51 19 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT[0..7] PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD[0..7] 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 3 4 5 6 7 8 9 10 87 88 89 90 91 92 93 94 VDD VSS VDDX0 VDDX1 VSSX0 VSSX1 XFC VDDPLL VSSPLL RESET XTAL EXTAL PE0/XIRQ PE1/IRQ PE2/R/W PE3/LSTRB PE4/ECLK PE5/MODA PE6/MODB PE7/ARST BKPD/TAGHI PS0/RxD0 PS1/RxD0 PS2/TxD1 PS3/TxD12 PS4/SDI/MISO PS5/SD0/MOSI PS6/SCK PS7/SS PT0/IOC0 PT1/IOC1 PT2/IOC2 PT3/IOC3 PT4/IOC4 PT5/IOC5 PT6/IOC6 PT7/IOC7 PJ0/KWJ0 PJ1/KWJ1 PJ2/KWJ2 PJ3/KWJ3 PJ5/KWJ4 PJ5/KWJ5 PJ6/KWJ6 PJ7/KWJ7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 U1 MC68HC812A4 PB0/ADDR00 PB1/ADDR01 PB2/ADDR02 PB3/ADDR03 PB4/ADDR04 PB5/ADDR05 PB6/ADDR06 PB7/ADDR07 PA0/ADDR08 PA1/ADDR09 PA2/ADDR10 PA3/ADDR11 PA4/ADDR12 PA5/ADDR13 PA6/ADDR14 PA7/ADDR15 PG0/ADDR16 PG1/ADDR17 PG2/ADDR18 PG3/ADDR19 PG4/ADDR20 PG5/ADDR21 PD0/KWD0/DATA0 PD1/KWD1/DATA1 PD2/KWD2/DATA2 PD3/KWD3/DATA3 PD4/KWD4/DATA4 PD5/KWD5/DATA5 PD6/KWD6/DATA6 PD7/KWD7/DATA7 PC0/DATA08 PC1/DATA09 PC2/DATA10 PC3/DATA11 PC4/DATA12 PC5/DATA13 PD6/DATA14 PC7/DATA15 PF0/CS0 PF1/CS1 PF2/CS2 PF3/CS3 PF4/CSD PF5/CSP0 PF6/CSP1 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 11 12 13 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 68 69 70 71 72 73 74 75 76 77 78 81 82 83 84 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF[0..7] PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH[0..7] A[0..21] R1 XFC R2 XTAL R3 EXTAL S1 A4_RESET PE[0..7] BKPTA JP2 1 2 3 4 5 6 C3 C4 RESETA PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 A0 A0 GROUND VDD HEADER 6 1 2 3 4 5 6 BKPTA D[0..15] PS[0..7] RESETA RSET MC34064 GND IN 2 3 1 U2 VCC PJ[0..7] C6 1.0 F C7 0.1 F C8 0.1 F C9 0.1 F Figure 1-4. Expanded Narrow Mode FLASH EEPROM Expansion Schematic (Sheet 1 of 3) MC68HC812A4 -- Rev. 3.0 40 General Description Advance Information MOTOROLA General Description Signal Descriptions A(0. . 21] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 PF5 PE2 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE WE VPP U3 AM27F010 D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21 D8 D9 D10 D11 D12 D13 D14 D15 D(0. . 15] PF[0. . 7] PE[0. . 7] Figure 1-4. Expanded Narrow Mode FLASH EEPROM Expansion Schematic (Sheet 2 of 3) D(0. . 15] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 U3 DS1230Y 11 12 13 15 16 17 18 19 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 D0 D1 D2 D3 D4 D5 D6 D7 A(0. . 21] PF6 PE2 20 27 22 CE WE OE PF[0. . 7] PE[0. . 7] Figure 1-4. Expanded Narrow Mode FLASH EEPROM Expansion Schematic (Sheet 3 of 3) Advance Information MOTOROLA General Description MC68HC812A4 -- Rev. 3.0 41 General Description MC68HC812A4 -- Rev. 3.0 42 General Description Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 2. Register Block 2.1 Contents 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2 Overview The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG15-REG11 in the INITRG register. INITRG establishes the upper five bits of the register block's 16-bit address. The register block occupies the first 512 bytes of the 2-Kbyte block. Figure 2-1 shows the default addressing. Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 43 Register Block 2.3 Register Map Addr. $0000 Register Name Port A Data Register Read: (PORTA) Write: See page 96. Reset: Port B Data Register Read: (PORTB) Write: See page 97. Reset: Port A Data Direction Read: Register (DDRA) Write: See page 96. Reset: Port B Data Direction Read: Register (DDRB) Write: See page 97. Reset: Port C Data Register Read: (PORTC) Write: See page 98. Reset: Port D Data Register Read: (PORTD) Write: See page 100. Reset: Bit 7 PA7 0 PB7 0 DDRA7 0 DDRB7 0 PC7 0 PD7 0 6 PA6 0 PB6 0 DDRA6 0 DDRB6 0 PC6 0 PD6 0 DDRC6 0 Bit 6 0 PE6 0 DDRE6 0 5 PA5 0 PB5 0 DDRA5 0 DDRB5 0 PC5 0 PD5 0 DDRC5 0 Bit 5 0 PE5 0 DDRE5 0 4 PA4 0 PB4 0 DDRA4 0 DDRB4 0 PC4 0 PD4 0 DDRC4 0 Bit 4 0 PD4 0 DDRE4 0 R 3 PA3 0 PB3 0 DDRA3 0 DDRB3 0 PC3 0 PD3 0 DDRC3 0 Bit 3 0 PD3 1 DDRE3 0 = Reserved 2 PA2 0 PB2 0 DDRA2 0 DDRB2 0 PC2 0 PD2 0 DDRC2 0 Bit 2 0 PD2 0 DDRE2 0 1 PA1 0 PB1 0 DDRA1 0 DDRB1 0 PC1 0 PD1 0 DDRC1 0 Bit 1 0 PD1 0 DDRE1 1 U = Unaffected Bit 0 PA0 0 PB0 0 DDRA0 0 DDRB0 0 PC0 0 PD0 0 DDRC0 0 Bit 0 0 PD0 0 DDRE0 1 $0001 $0002 $0003 $0004 $0005 $0006 Port C Data Direction Read: DDRC7 Register (DDRC) Write: See page 99. Reset: 0 Port D Data Direction Read: Register (DDRD) Write: See page 101. Reset: Port E Data Register Read: (PORTE) Write: See page 102. Reset: Port E Data Direction Read: Register (DDRE) Write: See page 103. Reset: Bit 7 0 PE7 0 DDRE7 0 $0007 $0008 $0009 = Unimplemented Figure 2-1. Register Map (Sheet 1 of 15) MC68HC812A4 -- Rev. 3.0 44 Register Block Advance Information MOTOROLA Register Block Register Map Addr. $000A Register Name Port E Assignment Read: Register (PEAR) Write: See page 104. Reset: Bit 7 ARSIE 0 6 PLLTE 0 MODB 0 PUPG 1 RDPH 0 R R RAM14 0 REG14 0 EE14 0 NDRC 0 RSWAI 0 0 0 5 PIPOE 1 MODA 0 PUPF 1 RDPG 0 R R RAM13 0 REG13 0 EE13 0 0 0 RSBCK 0 0 0 4 NECLK 0 ESTR 1 PUPE 1 RDPF 0 R R RAM12 0 REG12 0 EE12 1 0 0 0 0 0 0 R 3 LSTRE 1 IVIS 1 PUPD 1 RDPE 0 R R RAM11 1 REG11 0 0 0 0 0 RTBYP 0 0 0 = Reserved 2 RDWE 1 0 0 PUC 1 PRPD 0 R R 0 0 0 0 0 0 0 0 RTR2 0 0 0 1 0 0 EMD 1 PUPB 1 RDPC 0 R R 0 0 0 0 0 0 0 0 RTR1 0 0 0 U = Unaffected Bit 0 0 0 EME 1 PUPA 1 RDPAB 0 R R 0 0 0 0 EEON 1 0 0 RTR0 0 0 0 $000B Mode Register Read: SMODN (MODE) Write: See page 85. Reset: 0 Pullup Control Read: Register (PUCR) Write: See page 107. Reset: Reduced Drive Read: Register (RDRIV) Write: See page 108. Reset: Reserved Reserved RAM Initialization Read: Register (INITRM) Write: See page 88. Reset: Register Initialization Read: Register (INITRG) Write: See page 87. Reset: EEPROM Initialization Read: Register (INITEE) Write: See page 89. Reset: PUPH 1 RDPJ 0 R R RAM15 0 REG15 0 EE15 0 EWDIR 0 RTIE 0 RTIF 0 $000C $000D $000E $000F $0010 $0011 $0012 Miscellaneous Mapping Read: $0013 Control Register (MISC) Write: See page 89. Reset: Real-Tme Interrupt Read: $0014 Control Reg. (RTICTL) Write: See page 161. Reset: Real-Time Interrupt Flag Register (RTIFLG) $0015 See page 163. Read: Write: Reset: = Unimplemented Figure 2-1. Register Map (Sheet 2 of 15) Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 45 Register Block Addr. $0016 Register Name COP Control Register (COPCTL) See page 163. Read: Write: Reset: Bit 7 CME 0 0 Bit 7 0 R R IRQE 0 1 1 Bit 7 0 Bit 7 0 R R PH7 0 Bit 7 0 Bit 7 0 6 FCME 0 0 Bit 6 0 R R IRQEN 1 1 1 Bit 6 0 Bit 6 0 R R PH6 0 Bit 6 0 Bit 6 0 5 FCM 0 0 Bit 5 0 R R DLY 1 PSEL5 1 Bit 5 0 Bit 5 0 R R PH5 0 Bit 5 0 Bit 5 0 4 FCOP 0 0 Bit 4 0 R R 0 0 PSEL4 1 Bit 4 0 Bit 4 0 R R PH4 0 Bit 4 0 Bit 4 0 R 3 DISR 0 0 Bit 3 0 R R 0 0 PSEL3 0 Bit 3 0 Bit 3 0 R R PH3 0 Bit 3 0 Bit 3 0 = Reserved 2 CR2 1 0 Bit 2 0 R R 0 0 PSEL2 0 Bit 2 0 Bit 2 0 R R PH2 0 Bit 2 0 Bit 2 0 1 CR1 1 0 Bit 1 0 R R 0 0 PSEL1 1 Bit 1 0 Bit 1 0 R R PH1 0 Bit 1 0 Bit 1 0 U = Unaffected Bit 0 CR0 1 0 Bit 0 0 R R 0 0 0 0 Bit 0 0 Bit 0 0 R R PH0 0 Bit 0 0 Bit 0 0 $0017 $0018 $001D Arm/Reset COP Read: Register (COPRST) Write: See page 166. Reset: Reserved Reserved Interrupt Control Read: Register (INTCR) Write: See page 73. Reset: $001E Highest Priority I Read: $001F Interrupt Reg. (HPRIO) Write: See page 74. Reset: Port D Key Wakeup Read: $0020 Interrupt Enable Reg. Write: (KWIED) See page 145. Reset: Port D Key Wakeup Read: $0021 Flag Register (KWIFD) Write: See page 146. Reset: $0022 $0023 Reserved Reserved Port H Data Register Read: (PORTH) Write: See page 146. Reset: Port H Data Direction Read: Register (DDRH) Write: See page 147. Reset: $0024 $0025 Port H Key Wakeup Read: $0026 Interrupt Enable Reg. Write: (KWIEH) See page 147. Reset: = Unimplemented Figure 2-1. Register Map (Sheet 3 of 15) MC68HC812A4 -- Rev. 3.0 46 Register Block Advance Information MOTOROLA Register Block Register Map Addr. Register Name Bit 7 6 KWIFH6 0 PJ6 0 DDRJ6 0 KWIEJ6 0 KWIFJ6 0 KPOLJ6 0 PUPSJ6 0 PULEJ6 0 R PF6 0 0 0 5 KWIFH5 0 PJ5 0 DDRJ5 0 KWIEJ5 0 KWIFJ5 0 KPOLJ5 0 PUPSJ5 0 PULEJ5 0 R PF5 0 Bit 5 0 4 KWIFH4 0 PJ4 0 DDRJ4 0 KWIEJ4 0 KWIFJ4 0 KPOLJ4 0 PUPSJ4 0 PULEJ4 0 R PF4 0 Bit 4 0 R 3 KWIFH3 0 PJ3 0 DDRJ3 0 KWIEJ3 0 KWIFJ3 0 KPOLJ3 0 PUPSJ3 0 PULEJ3 0 R PF3 0 Bit 3 0 = Reserved 2 KWIFH2 0 PJ2 0 DDRJ2 0 KWIEJ2 0 KWIFJ2 0 KPOLJ2 0 PUPSJ2 0 PULEJ2 0 R PF2 0 Bit 2 0 1 KWIFH1 0 PJ1 0 DDRJ1 0 KWIEJ1 0 KWIFJ1 0 KPOLJ1 0 PUPSJ1 0 PULEJ1 0 R PF1 0 Bit 1 0 U = Unaffected Bit 0 KWIFH0 0 PJ0 0 DDRJ0 0 KWIEJ0 0 KWIFJ0 0 KPOLJ0 0 PUPSJ0 0 PULEJ0 0 R PF0 0 Bit 0 0 Port H Key Wakeup Read: KWIFH7 $0027 Flag Register (KWIFH) Write: See page 148. Reset: 0 $0028 Port J Data Register Read: (PORTJ) Write: See page 148. Reset: Port J Data Direction Read: Register (DDRJ) Write: See page 149. Reset: PJ7 0 DDRJ7 0 $0029 $002A Port J Key Wakeup Read: Interrupt Enable Write: KWIEJ7 Register (KWIEJ) 0 See page 149. Reset: Port J Key Wakeup Flag Read: KWIFJ7 $002B Register (KWIFJ) Write: See page 150. Reset: 0 Port J Key Wakeup Read: KPOLJ7 $002C Polarity Register Write: (KPOLJ) See page 150. Reset: 0 Port J Key Wakeup Read: Pullup/Pulldown Select Write: PUPSJ7 $002D Register (PUPSJ) 0 See page 151. Reset: Port J Key Wakeup Read: Pullup/Pulldown Enable Write: PULEJ7 $002E Register (PULEJ) 0 See page 152. Reset: $002F Reserved Port F Data Register Read: (PORTF) Write: See page 130. Reset: Port G Data Register Read: (PORTG) Write: See page 130. Reset: R 0 0 0 0 $0030 $0031 = Unimplemented Figure 2-1. Register Map (Sheet 4 of 15) Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 47 Register Block Addr. $0032 Register Name Port F Data Direction Read: Register (DDRF) Write: See page 131. Reset: Port G Data Direction Read: Register (DDRG) Write: See page 131. Reset: Data Page Register Read: (DPAGE) Write: See page 132. Reset: Bit 7 0 0 0 0 PD19 0 PPA21 0 PEA17 0 DWEN 0 0 0 R R R 0 0 0 0 0 0 6 DDRF6 0 0 0 PD18 0 PPA20 0 PEA16 0 PWEN 0 0 0 R R R CSP1E 0 CSP1FL 0 0 0 5 DDRF5 0 DDRG5 0 PD17 0 PPA19 0 PEA15 0 EWEN 0 A21E 0 R R R CSP0E 0 CSPA21 0 SRP1A 1 4 DDRF4 0 DDRG4 0 PD16 0 PPA18 0 PEA14 0 0 0 A20E 0 R R R CSDE 0 CSDHF 0 SRP1B 1 R 3 DDRF3 0 DDRG3 0 PD15 0 PPA17 0 PEA13 0 0 0 A19E 0 R R R CS3E 0 CS3EP 0 SRP0A 1 = Reserved 2 DDRF2 0 DDRG2 0 PD14 0 PPA16 0 PEA12 0 0 0 A18E 0 R R R CS2E 0 0 0 SRP0B 1 1 DDRF1 0 DDRG1 0 PD13 0 PPA15 0 PEA11 0 0 0 A17E 0 R R R CS1E 0 0 0 STRDA 1 U = Unaffected Bit 0 DDRF0 0 DDRG0 0 PD12 0 PPA14 0 PEA10 0 0 0 A16E 0 R R R CS0E 0 0 0 STRDB 1 $0033 $0034 Program Page Register Read: $0035 (PPAGE) Write: See page 132. Reset: $0036 Extra Page Register Read: (EPAGE) Write: See page 133. Reset: Window Definition Read: Register (WINDEF) Write: See page 133. Reset: $0037 Memory Expansion Read: $0038 Assignment Register Write: (MXAR) See page 134. Reset: $0039 $003A $003B Reserved Reserved Reserved Chip-Select Control Read: Register 0 (CSCTL0) Write: See page 136. Reset: Chip-Select Control Read: Register 1 (CSCTL1) Write: See page 138. Reset: Chip-Select Stretch Read: Register 0 (CSSTR0) Write: See page 139. Reset: $003C $003D $003E = Unimplemented Figure 2-1. Register Map (Sheet 5 of 15) MC68HC812A4 -- Rev. 3.0 48 Register Block Advance Information MOTOROLA Register Block Register Map Addr. $003F Register Name Chip-Select Stretch Read: Register 1 (CSSTR1) Write: See page 139. Reset: Loop Divider Register Read: High (LDVH) Write: See page 171. Reset: Loop Divider Register Read: Low (LDVL) Write: See page 171. Reset: Reference Divider Read: Register High (RDVH) Write: See page 172. Reset: Reference Divider Read: Register Low (RDVL) Write: See page 172. Reset: Reserved Reserved Reserved Bit 7 STR3A 0 0 0 LDV7 1 0 0 RDV7 1 R R R LCKF 0 R R 0 0 0 0 6 STR3B 0 0 0 LDV6 1 0 0 RDV6 1 R R R PLLON 0 R R 0 0 0 0 5 STR2A 1 0 0 LDV5 1 0 0 RDV5 1 R R R PLLS 0 R R 0 0 0 0 4 STR2B 1 0 0 LDV4 1 0 0 RDV4 1 R R R BCSC 0 R R 0 0 0 0 R 3 STR1A 1 LDV11 1 LDV3 1 RDV11 1 RDV3 1 R R R BCSB 0 R R 0 0 0 0 = Reserved 2 STR1B 1 LDV10 1 LDV2 1 RDV10 1 RDV2 1 R R R BCSA 0 R R 0 0 0 0 1 STR0A 1 LDV9 1 LDV1 1 RDV9 1 RDV1 1 R R R MCSB 0 R R 0 0 0 0 U = Unaffected Bit 0 STR0B 1 LDV8 1 LDV0 1 RDV8 1 RDV0 1 R R R MCSA 0 R R 0 0 0 0 $0040 $0041 $0042 $0043 $0044 $0045 $0046 Clock Control Register Read: $0047 (CLKCTL) Write: See page 173. Reset: $0048 $005F Reserved Reserved ATD Control Register 0 Read: $0060 (ATDCTL0) Write: See page 291. Reset: ATD Control Register 1 Read: $0061 (ATDCTL1) Write: See page 291. Reset: = Unimplemented Figure 2-1. Register Map (Sheet 6 of 15) Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 49 Register Block Addr. Register Name Bit 7 ADPU 0 0 0 0 0 0 0 SCF 0 CCF7 0 SAR9 0 SAR1 0 R R PAD7 0 6 AFFC 0 0 0 SMP1 0 S8CM 0 0 0 CCF6 0 SAR8 0 SAR0 0 R R PAD6 0 ADRxH6 5 AWAI 0 0 0 SMP0 0 SCAN 0 0 0 CCF5 0 SAR7 0 RST 0 R R PAD5 0 ADRxH5 4 0 0 0 0 PRS4 0 MULT 0 0 0 CCF4 0 SAR6 0 TSTOUT 0 R R PAD4 0 ADRxH4 3 0 0 0 0 PRS3 0 CD 0 0 0 CCF3 0 SAR5 0 TST3 0 R R PAD3 0 ADRxH3 2 0 0 0 0 PRS2 0 CC 0 CC2 0 CCF2 0 SAR4 0 TST2 0 R R PAD2 0 ADRxH2 1 ASCIE 0 FRZ1 0 PRS1 0 CB 0 CC1 0 CCF1 0 SAR3 0 TST1 0 R R PAD1 0 ADRxH1 Bit 0 ASCIF 0 FRZ0 0 PRS0 1 CA 0 CC0 0 CCF0 0 SAR2 0 TST0 0 R R PAD0 0 ADRxH0 ATD Control Register 2 Read: $0062 (ATDCTL2) Write: See page 292. Reset: ATD Control Register 3 Read: $0063 (ATDCTL3) Write: See page 293. Reset: ATD Control Register 4 Read: $0064 (ATDCTL4) Write: See page 294. Reset: ATD Control Register 5 Read: $0065 (ATDCTL5) Write: See page 296. Reset: $0066 ATD Status Register 1 Read: (ATDSTAT1) Write: See page 298. Reset: ATD Status Register 2 Read: (ATDSTAT2) Write: See page 298. Reset: ATD Test Register 1 Read: (ATDTEST1) Write: See page 299. Reset: ATD Test Register 2 Read: (ATDTEST2) Write: See page 299. Reset: Reserved Reserved Port AD Data Input Read: Register (PORTAD) Write: See page 302. Reset: $0067 $0068 $0069 $006A $006E $006F $0070 ATD Result Register 0 Read: ADRxH7 (ADR0H) Write: See page 300. Reset: Indeterminate = Unimplemented R = Reserved U = Unaffected Figure 2-1. Register Map (Sheet 7 of 15) MC68HC812A4 -- Rev. 3.0 50 Register Block Advance Information MOTOROLA Register Block Register Map Addr. $0071 Register Name Reserved Bit 7 R 6 R ADRxH6 5 R ADRxH5 4 R ADRxH4 3 R ADRxH3 2 R ADRxH2 1 R ADRxH1 Bit 0 R ADRxH0 $0072 $0073 ATD Result Register 1 Read: ADRxH7 (ADR1H) Write: See page 300. Reset: Reserved R Indeterminate R ADRxH6 R ADRxH5 R ADRxH4 R ADRxH3 R ADRxH2 R ADRxH1 R ADRxH0 $0074 $0075 ATD Result Register 2 Read: ADRxH7 (ADR2H) Write: See page 300. Reset: Reserved R Indeterminate R ADRxH6 R ADRxH5 R ADRxH4 R ADRxH3 R ADRxH2 R ADRxH1 R ADRxH0 $0076 $0077 ATD Result Register 3 Read: ADRxH7 (ADR3H) Write: See page 300. Reset: Reserved R Indeterminate R ADRxH6 R ADRxH5 R ADRxH4 R ADRxH3 R ADRxH2 R ADRxH1 R ADRxH0 $0078 $0079 ATD Result Register 4 Read: ADRxH7 (ADR4H) Write: See page 300. Reset: Reserved R Indeterminate R ADRxH6 R ADRxH5 R ADRxH4 R ADRxH3 R ADRxH2 R ADRxH1 R ADRxH0 $007A $007B ATD Result Register 5 Read: ADRxH7 (ADR5H) Write: See page 300. Reset: Reserved R Indeterminate R ADRxH6 R ADRxH5 R ADRxH4 R ADRxH3 R ADRxH2 R ADRxH1 R ADRxH0 $007C $007D ATD Result Register 6 Read: ADRxH7 (ADR6H) Write: See page 300. Reset: Reserved R Indeterminate R ADRxH6 R ADRxH5 R ADRxH4 R ADRxH3 R ADRxH2 R ADRxH1 R ADRxH0 $007E $007F ATD Result Register 7 Read: ADRxH7 (ADR7H) Write: See page 300. Reset: Reserved R Indeterminate R R R R R = Reserved R R U = Unaffected R = Unimplemented Figure 2-1. Register Map (Sheet 8 of 15) Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 51 Register Block Addr. $0080 Register Name Timer IC/OC Select Read: Register (TIOS) Write: See page 186. Reset: Timer Compare Force Read: Register (CFORC) Write: See page 187. Reset: Bit 7 IOS7 0 FOC7 0 6 IOS6 0 FOC6 0 OC7M6 0 OC7D6 0 Bit 14 0 BIt 6 0 TSWAI 0 R OL7 0 OL3 0 EDG7A 0 5 IOS5 0 FOC5 0 OC7M5 0 OC7D5 0 Bit 13 0 Bit 5 0 TSBCK 0 R OM6 0 OM2 0 EDG6B 0 4 IOS4 0 FOC4 0 OC7M4 0 OC7D4 0 Bit 12 0 Bit 4 0 TFFCA 0 R OL6 0 OL2 0 EDG6A 0 R 3 IOS3 0 FOC3 0 OC7M3 0 OC7D3 0 Bit 11 0 Bit 3 0 0 0 R OM5 0 OM1 0 EDG5B 0 = Reserved 2 IOS2 0 FOC2 0 OC7M2 0 OC7D2 0 Bit 10 0 Bit 2 0 0 0 R OL5 0 OL1 0 EDG5A 0 1 IOS1 0 FOC1 0 OC7M1 0 OC7D1 0 Bit 9 0 Bit 1 0 0 0 R OM4 0 OM0 0 EDG4B 0 U = Unaffected Bit 0 IOS0 0 FOC0 0 OC7M0 0 OC7D0 0 Bit 8 0 Bit 0 0 0 0 R OL4 0 OL0 0 EDG4A 0 $0081 $0082 Timer Output Read: Compare 7 Mask Write: OC7M7 Register (OC7M) 0 See page 187. Reset: Timer Output Read: Compare 7 Data Write: Register (OC7D) See page 188. Reset: OC7D7 0 Bit 15 0 Bit 7 0 TEN 0 R OM7 0 OM3 0 EDG7B 0 $0083 Timer Counter Register Read: $0084 High (TCNTH) Write: See page 189. Reset: Timer Counter Register Read: $0085 Low (TCNTL) Write: See page 189. Reset: $0086 $0087 Timer System Control Read: Register (TSCR) Write: See page 190. Reset: Reserved Timer Control Read: Register 1 (TCTL1) Write: See page 192. Reset: Timer Control Read: Register 2 (TCTL2) Write: See page 192. Reset: Timer Control Read: Register 3 (TCTL3) Write: See page 193. Reset: $0088 $0089 $008A = Unimplemented Figure 2-1. Register Map (Sheet 9 of 15) MC68HC812A4 -- Rev. 3.0 52 Register Block Advance Information MOTOROLA Register Block Register Map Addr. $008B Register Name Timer Control Read: Register 4 (TCTL4) Write: See page 193. Reset: Bit 7 EDG3B 0 C7I 0 TOI 0 C7F 0 TOF 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 6 EDG3A 0 C6I 0 0 0 C6F 0 0 0 Bit 14 0 Bit 6 0 Bit 14 0 Bit 6 0 Bit 14 0 Bit 6 0 5 EDG2B 0 C5I 0 PUPT 1 C5F 0 0 0 Bit 13 0 Bit 5 0 Bit 13 0 Bit 5 0 Bit 13 0 Bit 5 0 4 EDG2A 0 C4I 0 RDPT 1 C4F 0 0 0 Bit 12 0 Bit 4 0 Bit 12 0 Bit 4 0 Bit 12 0 Bit 4 0 R 3 EDG1B 0 C3I 0 TCRE 0 C3F 0 0 0 Bit 11 0 Bit 3 0 Bit 11 0 Bit 3 0 Bit 11 0 Bit 3 0 = Reserved 2 EDG1A 0 C2I 0 PR2 0 C2F 0 0 0 Bit 10 0 Bit 2 0 Bit 10 0 Bit 2 0 Bit 10 0 Bit 2 0 1 EDG0B 0 C1I 0 PR1 0 C1F 0 0 0 Bit 9 0 Bit 1 0 Bit 9 0 Bit 1 0 Bit 9 0 Bit 1 0 U = Unaffected Bit 0 EDG0A 0 C0I 0 PR0 0 C0F 0 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Timer Mask Register 1 Read: $008C (TMSK1) Write: See page 194. Reset: Timer Mask Register 2 Read: $008D (TMSK2) Write: See page 194. Reset: $008E Timer Flag Register 1 Read: (TFLG1) Write: See page 196. Reset: Timer Flag Register 2 Read: (TFLG2) Write: See page 196. Reset: Timer Channel 0 Read: Register High (TC0H) Write: See page 197. Reset: Timer Channel 0 Read: Register Low (TC0L) Write: See page 197. Reset: Timer Channel 1 Read: Register High (TC1H) Write: See page 197. Reset: Timer Channel 1 Read: Register Low (TC1L) Write: See page 197. Reset: Timer Channel 2 Read: Register High (TC2H) Write: See page 197. Reset: Timer Channel 2 Read: Register Low (TC2L) Write: See page 197. Reset: $008F $0090 $0091 $0092 $0093 $0094 $0095 = Unimplemented Figure 2-1. Register Map (Sheet 10 of 15) Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 53 Register Block Addr. $0096 Register Name Timer Channel 3 Read: Register High (TC3H) Write: See page 197. Reset: Timer Channel 3 Read: Register Low (TC3L) Write: See page 197. Reset: Timer Channel 4 Read: Register High (TC4H) Write: See page 197. Reset: Timer Channel 4 Read: Register Low (TC4L) Write: See page 197. Reset: Timer Channel 5 Read: Register High (TC5H) Write: See page 197. Reset: Timer Channel 5 Read: Register Low (TC5L) Write: See page 197. Reset: Timer Channel 6 Read: Register High (TC6H) Write: See page 197. Reset: Timer Channel 6 Read: Register Low (TC6L) Write: See page 197. Reset: Timer Channel 7 Read: Register High (TC7H) Write: See page 197. Reset: Timer Channel 7 Read: Register Low (TC7L) Write: See page 197. Reset: Pulse Accumulator Read: Control Register Write: (PACTL) See page 198. Reset: Bit 7 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 0 0 6 Bit 14 0 Bit 6 0 Bit 14 0 Bit 6 0 Bit 14 0 Bit 6 0 Bit 14 0 Bit 6 0 Bit 14 0 Bit 6 0 PAEN 0 5 Bit 13 0 Bit 5 0 Bit 13 0 Bit 5 0 Bit 13 0 Bit 5 0 Bit 13 0 Bit 5 0 Bit 13 0 Bit 5 0 PAMOD 0 4 Bit 12 0 Bit 4 0 Bit 12 0 Bit 4 0 Bit 12 0 Bit 4 0 Bit 12 0 Bit 4 0 Bit 12 0 Bit 4 0 PEDGE 0 R 3 Bit 11 0 Bit 3 0 Bit 11 0 Bit 3 0 Bit 11 0 Bit 3 0 Bit 11 0 Bit 3 0 Bit 11 0 Bit 3 0 CLK1 0 = Reserved 2 Bit 10 0 Bit 2 0 Bit 10 0 Bit 2 0 Bit 10 0 Bit 2 0 Bit 10 0 Bit 2 0 Bit 10 0 Bit 2 0 CLK0 0 1 Bit 9 0 Bit 1 0 Bit 9 0 Bit 1 0 Bit 9 0 Bit 1 0 Bit 9 0 Bit 1 0 Bit 9 0 Bit 1 0 PAOVI 0 U = Unaffected Bit 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 PAI 0 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F $00A0 = Unimplemented Figure 2-1. Register Map (Sheet 11 of 15) MC68HC812A4 -- Rev. 3.0 54 Register Block Advance Information MOTOROLA Register Block Register Map Addr. Register Name Bit 7 Bit 0 0 Bit 15 0 Bit 7 0 R R 0 0 PT7 6 0 0 Bit 14 0 Bit 6 0 R R 0 0 PT6 5 0 0 Bit 13 0 Bit 5 0 R R 0 0 PT5 4 0 0 Bit 12 0 Bit 4 0 R R 0 0 PT4 3 0 0 Bit 11 0 Bit 3 0 R R 0 0 PT3 2 0 0 Bit 10 0 Bit 2 0 R R 0 0 PT2 1 PAOVF 0 Bit 9 0 Bit 1 0 R R TCBYP 0 PT1 Bit 0 PAIF 0 Bit 8 0 Bit 0 0 R R PCBYP 0 PT0 Pulse Accumulator Flag Read: $00A1 Register (PAFLG) Write: See page 200. Reset: $00A2 Pulse Accumulator Read: Counter Register High Write: (PACNTH) See page 201. Reset: Pulse Accumulator Read: Counter Register Low Write: (PACNTL) See page 201. Reset: Reserved Reserved Timer Test Register Read: (TIMTST) Write: See page 202. Reset: Timer Port Data Read: Register (PORTT) Write: See page 206. Reset: Timer Port Data Read: Direction Register Write: (DDRT) See page 207. Reset: Reserved Reserved SCI 0 Baud Rate Read: Register High Write: (SC0BDH) See page 249. Reset: $00A3 $00A4 $00AC $00AD $00AE Unaffected by reset Bit 7 0 R R BTST 0 SBR7 0 Bit 6 0 R R BSPL 0 SBR6 0 Bit 5 0 R R BRLD 0 SBR5 0 Bit 4 0 R R SBR12 0 SBR4 0 R Bit 3 0 R R SBR11 0 SBR3 0 = Reserved Bit 2 0 R R SBR10 0 SBR2 1 Bit 1 0 R R SBR9 0 SBR1 0 U = Unaffected Bit 0 0 R R SBR8 0 SBR0 0 $00AF $00B0 $00BF $00C0 SCI 0 Baud Rate Read: $00C1 Register Low (SC0BDL) Write: See page 249. Reset: = Unimplemented Figure 2-1. Register Map (Sheet 12 of 15) Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 55 Register Block Addr. $00C2 Register Name Bit 7 6 WOMS 0 TCIE 0 TC 1 0 0 T8 5 RSRC 0 RIE 0 RDRF 0 0 0 0 4 M 0 ILIE 0 IDLE 0 0 0 0 3 WAKE 0 TE 0 OR 0 0 0 0 2 ILT 0 RE 0 NF 0 0 0 0 1 PE 0 RWU 0 FE 0 0 0 0 Bit 0 PT 0 SBK 0 PF 0 RAF 0 0 SCI 0 Control Read: LOOPS Register 1 (SC0CR1) Write: See page 250. Reset: 0 SCI 0 Control Read: Register 2 (SC0CR2) Write: See page 252. Reset: SCI 0 Status Read: Register 1 (SC0SR1) Write: See page 254. Reset: SCI 0 Status Read: Register 2 (SC0SR2) Write: See page 256. Reset: SCI 0 Data Register Read: High (SC0DRH) Write: See page 257. Reset: SCI 0 Data Register Read: Low (SC0DRL) Write: See page 257. Reset: SCI 1 Baud Rate Read: Register High Write: (SC1BDH) See page 249. Reset: TIE 0 TDRE 1 0 0 R8 $00C3 $00C4 $00C5 $00C6 Unaffected by reset R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 $00C7 Unaffected by reset BTST 0 SBR7 0 BSPL 0 SBR6 0 WOMS 0 TCIE 0 TC 1 BRLD 0 SBR5 0 RSRC 0 RIE 0 RDRF 0 SBR12 0 SBR4 0 M 0 ILIE 0 IDLE 0 R SBR11 0 SBR3 0 WAKE 0 TE 0 OR 0 = Reserved SBR10 0 SBR2 1 ILT 0 RE 0 NF 0 SBR9 0 SBR1 0 PE 0 RWU 0 FE 0 U = Unaffected SBR8 0 SBR0 0 PT 0 SBK 0 PF 0 $00C8 SCI 1 Baud Rate Read: $00C9 Register Low (SC1BDL) Write: See page 249. Reset: SCI 1 Control Register Read: LOOPS $00CA 1 (SC1CR1) Write: See page 250. Reset: 0 SCI 1 Control Register Read: $00CB 2 (SC1CR2) Write: See page 252. Reset: SCI 1 Status Register 1 Read: $00CC (SC1SR1) Write: See page 254. Reset: TIE 0 TDRE 1 = Unimplemented Figure 2-1. Register Map (Sheet 13 of 15) MC68HC812A4 -- Rev. 3.0 56 Register Block Advance Information MOTOROLA Register Block Register Map Addr. Register Name Bit 7 0 0 R8 6 0 0 T8 5 0 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 Bit 0 RAF 0 0 SCI 1 Status Register 2 Read: $00CD (SC1SR2) Write: See page 256. Reset: $00CE SCI 1 Data Register Read: High (SC1DRH) Write: See page 257. Reset: SCI 1 Data Register Read: Low (SC1DRL) Write: See page 257. Reset: Unaffected by reset R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 $00CF Unaffected by reset SPIE 0 0 0 0 0 SPIF 0 R Bit 7 SPE 0 0 0 0 0 WCOL 0 R Bit 6 SWOM 0 0 0 0 0 0 0 R Bit 5 MSTR 0 0 0 0 0 MODF 0 R Bit 4 CPOL 0 PUPS 1 0 0 0 0 R Bit 3 CPHA 1 RDS 0 SPR2 0 0 0 R Bit 2 SSOE 0 0 0 SPR1 0 0 0 R Bit 1 LSBF 0 SPC0 0 SPR0 0 0 0 R Bit 0 SPI 0 Control Register Read: $00D0 1 (SP0CR1) Write: See page 273. Reset: SPI 0 Control Register Read: $00D1 2 (SP0CR2) Write: See page 275. Reset: SPI Baud Rate Register Read: $00D2 (SP0BR) Write: See page 276. Reset: $00D3 $00D4 SPI Status Register Read: (SP0SR) Write: See page 277. Reset: Reserved SPI Data Register Read: (SP0DR) Write: See page 278. Reset: Port S Data Register Read: (PORTS) Write: See page 219. Reset: Port S Data Direction Read: Register (DDRS) Write: See page 220. Reset: $00D5 Unaffected by reset PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 $00D6 Unaffected by reset DDRS7 0 DDRS6 0 DDRS5 0 DDRS4 0 R DDRS3 0 = Reserved DDRS2 0 DDRS1 0 U = Unaffected DDRS0 0 $00D7 = Unimplemented Figure 2-1. Register Map (Sheet 14 of 15) Advance Information MOTOROLA Register Block MC68HC812A4 -- Rev. 3.0 57 Register Block Addr. $00D8 $00EF Register Name Reserved Reserved Bit 7 R R 1 1 1 1 6 R R 1 1 BPROT6 1 EEVEN 0 0 0 R R 5 R R 1 1 BPROT5 1 MARG 0 0 0 R R 4 R R 1 1 BPROT4 1 EECPD 0 BYTE 0 R R R 3 R R 1 1 BPROT3 1 EECPRD 0 ROW 0 R R = Reserved 2 R R EESWAI 1 BPROT2 1 0 0 ERASE 0 R R 1 R R PROTLCK 0 BPROT1 1 EECPM 0 EELAT 0 R R U = Unaffected Bit 0 R R EERC 0 BPROT0 1 0 0 EEPGM 0 R R EEPROM Configuration Read: $00F0 Register (EEMCR) Write: See page 114. Reset: EEPROM Block Protect Read: $00F1 Register (EEPROT) Write: See page 115. Reset: EEPROM Test Register Read: EEODD $00F2 (EETST) Write: See page 116. Reset: 0 EEPROM Programming Read: $00F3 Register (EEPROG) Write: See page 117. Reset: $00F4 $01FF Reserved Reserved R BULKP 1 R = Unimplemented Figure 2-1. Register Map (Sheet 15 of 15) 2.4 Modes of Operation PORTA, PORTB, PORTC, and data direction registers DDRA, DDRB, and DDRC are not in the map in expanded and peripheral modes. PEAR, MODE, PUCR, and RDRIV are not in the map in peripheral mode. When EMD is set: * * * PORTD and DDRD are not the map in wide expanded modes, peripheral mode, and narrow special expanded mode. PORTE and DDRE are not in the map in peripheral mode and expanded modes. KWIED and KWIFD are not in the map in wide expanded modes and narrow special expanded mode. Advance Information Register Block MOTOROLA MC68HC812A4 -- Rev. 3.0 58 Advance Information -- MC68HC812A4 Section 3. Central Processor Unit (CPU12) 3.1 Contents 3.2 3.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.4.1 Accumulators A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.4.2 Accumulator D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.4.3 Index Registers X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.4.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.4.5 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.4.6 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.5 3.6 3.7 3.8 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.2 Overview The CPU12 is a high-speed, 16-bit processor unit. It has full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set. The CPU12 allows instructions with odd byte counts, including many single-byte instructions. This provides efficient use of ROM space. An instruction queue buffers program information so the CPU always has immediate access to at least three bytes of machine code at the start of every instruction. The CPU12 also offers an extensive set of indexed addressing capabilities. Advance Information MOTOROLA Central Processor Unit (CPU12) MC68HC812A4 -- Rev. 3.0 59 Central Processor Unit (CPU12) 3.3 Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. See Figure 3-1. 7 15 A 0 D 7 B 0 0 8-BIT ACCUMULATORS A AND B 16-BIT DOUBLE ACCUMULATOR D (A : B) 15 X 0 INDEX REGISTER X 15 Y 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER S X H I N Z V C CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE IRQ INTERRUPT MASK (DISABLE) HALF-CARRY FOR BCD ARITHMETIC XIRQ INTERRUPT MASK (DISABLE) STOP DISABLE (IGNORE STOP OPCODES) Figure 3-1. Programming Model 3.4 CPU Registers This section describes the CPU registers. MC68HC812A4 -- Rev. 3.0 60 Central Processor Unit (CPU12) Advance Information MOTOROLA Central Processor Unit (CPU12) CPU Registers 3.4.1 Accumulators A and B Accumulators A and B are general-purpose 8-bit accumulators that contain operands and results of arithmetic calculations or data manipulations. Bit 7 A7 Reset: 6 A6 5 A5 4 A4 3 A3 2 A2 1 A1 Bit 0 A0 Unaffected by reset Figure 3-2. Accumulator A (A) Bit 7 B7 Reset: 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 Bit 0 B0 Unaffected by reset Figure 3-3. Accumulator B (B) 3.4.2 Accumulator D Accumulator D is the concatenation of accumulators A and B. Some instructions treat the combination of these two 8-bit accumulators as a 16-bit double accumulator. Bit 15 D15 (A7) Reset: 14 D14 (A6) 13 D13 (A5) 12 D12 (A4) 11 D11 (A3) 10 D10 (A2) 9 D9 (A1) 8 D8 (A0) 7 D7 (B7) 6 D6 (B6) 5 D5 (B5) 4 D4 (B4) 3 D3 (B3) 2 D2 (B2) 1 D1 (B1) Bit 0 D0 (B0) Unaffected by reset Figure 3-4. Accumulator D (D) Advance Information MOTOROLA Central Processor Unit (CPU12) MC68HC812A4 -- Rev. 3.0 61 Central Processor Unit (CPU12) 3.4.3 Index Registers X and Y Index registers X and Y are used for indexed addressing. Indexed addressing adds the value in an index register to a constant or to the value in an accumulator to form the effective address of the operand. Index registers X and Y can also serve as temporary data storage locations. Bit 15 X15 Reset: 14 X14 13 X13 12 X12 11 X11 10 X10 9 X9 8 X8 7 X7 6 X6 5 X5 4 X4 3 X3 2 X2 1 X1 Bit 0 X0 Unaffected by reset Figure 3-5. Index Register X (X) Bit 15 Y15 Reset: 14 Y14 13 Y13 12 Y12 11 Y11 10 Y10 9 Y9 8 Y8 7 Y7 6 Y6 5 Y5 4 Y4 3 Y3 2 Y2 1 Y1 Bit 0 Y0 Unaffected by reset Figure 3-6. Index Register Y (Y) 3.4.4 Stack Pointer The stack pointer (SP) contains the last stack address used. The CPU12 supports an automatic program stack that is used to save system context during subroutine calls and interrupts. The stack pointer can also serve as a temporary data storage location or as an index register for indexed addressing. Bit 15 14 13 12 11 10 9 SP9 8 SP8 7 SP7 6 SP6 5 SP5 4 SP4 3 SP3 2 SP2 1 SP1 Bit 0 SP0 SP15 SP14 SP13 SP12 SP11 SP10 Reset: Unaffected by reset Figure 3-7. Stack Pointer (SP) MC68HC812A4 -- Rev. 3.0 62 Central Processor Unit (CPU12) Advance Information MOTOROLA Central Processor Unit (CPU12) CPU Registers 3.4.5 Program Counter The program counter contains the address of the next instruction to be executed. The program counter can also serve as an index register in all indexed addressing modes except autoincrement and autodecrement. Bit 15 14 13 12 11 10 9 SP9 8 SP8 7 SP7 6 SP6 5 SP5 4 SP4 3 SP3 2 SP2 1 SP1 Bit 0 SP0 SP15 SP14 SP13 SP12 SP11 SP10 Reset: Unaffected by reset Figure 3-8. Program Counter (PC) 3.4.6 Condition Code Register Bit 7 S Reset: U U = Unaffected 6 X 1 5 H U 4 I 1 3 N U 2 Z U 1 V U Bit 0 C U Figure 3-9. Condition Code Register (CCR) S -- Stop Disable Bit Setting the S bit disables the STOP instruction. X -- XIRQ Interrupt Mask Bit Setting the X bit masks interrupt requests from the XIRQ pin. H -- Half-Carry Flag The H flag is used only for BCD arithmetic operations. It is set when an ABA, ADD, or ADC instruction produces a carry from bit 3 of accumulator A. The DAA instruction uses the H flag and the C flag to adjust the result to correct BCD format. Advance Information MOTOROLA Central Processor Unit (CPU12) MC68HC812A4 -- Rev. 3.0 63 Central Processor Unit (CPU12) I -- Interrupt Mask Bit Setting the I bit disables maskable interrupt sources. N -- Negative Flag The N flag is set when the result of an operation is less than 0. Z -- Zero Flag The Z flag is set when the result of an operation is all 0s. V -- Two's Complement Overflow Flag The V flag is set when a two's complement overflow occurs. C -- Carry/Borrow Flag The C flag is set when an addition or subtraction operation produces a carry or borrow. 3.5 Data Types The CPU12 supports four data types: 1. Bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. There are no special requirements for alignment of instructions or operands. MC68HC812A4 -- Rev. 3.0 64 Central Processor Unit (CPU12) Advance Information MOTOROLA Central Processor Unit (CPU12) Addressing Modes 3.6 Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. Table 3-1 is a summary of the available addressing modes. Table 3-1. Addressing Mode Summary Addressing Mode Inherent Immediate Direct Extended Relative Indexed (5-bit offset) Indexed (auto pre-decrement) Indexed (auto pre-increment) Indexed (auto post-decrement) Indexed (auto post-increment) Indexed (accumulator offset) Indexed (9-bit offset) Indexed (16-bit offset) Indexed-indirect (16-bit offset) Indexed-indirect (D accumulator offset) Source Format INST INST #opr8i or INST #opr16i INST opr8a INST opr16a INST rel8 or INST rel16 INST oprx5,xysp INST oprx3,-xys INST oprx3,+xys INST oprx3,xys- INST oprx3,xys+ INST abd,xysp INST oprx9,xysp INST oprx16,xysp INST [oprx16,xysp] Abbreviation INH IMM DIR EXT REL IDX IDX IDX IDX IDX IDX IDX1 IDX2 [IDX2] Description Operands (if any) are in CPU registers. Operand is included in instruction stream. 8- or 16-bit size implied by context Operand is the lower 8 bits of an address in the range $0000-$00FF. Operand is a 16-bit address An 8-bit or 16-bit relative offset from the current pc is supplied in the instruction. 5-bit signed constant offset from x, y, sp, or pc Auto pre-decrement x, y, or sp by 1 ~ 8 Auto pre-increment x, y, or sp by 1 ~ 8 Auto post-decrement x, y, or sp by 1 ~ 8 Auto post-increment x, y, or sp by 1 ~ 8 Indexed with 8-bit (A or B) or 16-bit (D) accumulator offset from x, y, sp, or pc 9-bit signed constant offset from x, y, sp, or pc (lower 8-bits of offset in one extension byte) 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) Pointer to operand is found at... 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) Pointer to operand is found at... x, y, sp, or pc plus the value in D INST [D,xysp] [D,IDX] Advance Information MOTOROLA Central Processor Unit (CPU12) MC68HC812A4 -- Rev. 3.0 65 Central Processor Unit (CPU12) 3.7 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The postbyte and extensions do these tasks: * * * * Specify which index register is used Determine whether a value in an accumulator is used as an offset Enable automatic pre- or post-increment or decrement Specify use of 5-bit, 9-bit, or 16-bit signed offsets Table 3-2. Summary of Indexed Operations Postbyte Source Code Code (xb) Syntax ,r rr0nnnnn n,r -n,r Comments rr: 00 = X, 01 = Y, 10 = SP, 11 = PC 5-bit constant offset n = -16 to +15 r can specify x, y, sp, or pc Constant offset (9- or 16-bit signed) z:0 = 9-bit with sign in LSB of postbyte(s) 1 = 16-bit if z = s = 1, 16-bit offset indexed-indirect (see below) rr can specify x, y, sp, or pc 16-bit offset indexed-indirect rr can specify x, y, sp, or pc Auto pre-decrement/increment or Auto post-decrement/increment; p = pre-(0) or post-(1), n = -8 to -1, +1 to +8 rr can specify x, y, or sp (pc not a valid choice) Accumulator offset (unsigned 8-bit or 16-bit) aa:00 = A 01 = B 10 = D (16-bit) 11 = see accumulator D offset indexed-indirect rr can specify x, y, sp, or pc Accumulator D offset indexed-indirect rr can specify x, y, sp, or pc 111rr0zs n,r -n,r 111rr011 [n,r] n,-r n,+r rr1pnnnn n,r- n,r+ A,r 111rr1aa B,r D,r 111rr111 [D,r] MC68HC812A4 -- Rev. 3.0 66 Central Processor Unit (CPU12) Advance Information MOTOROLA Central Processor Unit (CPU12) Opcodes and Operands 3.8 Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the opcode map. Opcodes on the second page are preceded by an additional byte with the value $18. To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop primitives. Extension bytes contain additional program information such as addresses, offsets, and immediate data. Advance Information MOTOROLA Central Processor Unit (CPU12) MC68HC812A4 -- Rev. 3.0 67 Central Processor Unit (CPU12) MC68HC812A4 -- Rev. 3.0 68 Central Processor Unit (CPU12) Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 4. Resets and Interrupts 4.1 Contents 4.2 4.3 4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.5 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.5.1 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.5.2 Highest Priority I Interrupt Register . . . . . . . . . . . . . . . . . . .74 4.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.6.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.6.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.6.3 COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.6.4 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.7 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.7.1 Operating Mode and Memory Map. . . . . . . . . . . . . . . . . . . .76 4.7.2 Clock and Watchdog Control Logic . . . . . . . . . . . . . . . . . . .76 4.7.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.7.4 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.7.5 Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.7 Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.8 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Advance Information MOTOROLA Resets and Interrupts MC68HC812A4 -- Rev. 3.0 69 Resets and Interrupts 4.2 Introduction Resets and interrupts are exceptions. Each exception has a 16-bit vector that points to the memory location of the associated exception-handling routine. Vectors are stored in the upper 128 bytes of the standard 64-Kbyte address map. The six highest vector addresses are used for resets and non-maskable interrupt sources. The remainder of the vectors are used for maskable interrupts, and all must be initialized to point to the address of the appropriate service routine. 4.3 Exception Priority A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. Six sources are not maskable. The remaining sources are maskable and any one of them can be given priority over other maskable interrupts. The priorities of the non-maskable sources are: 1. POR (power-on reset) or RESET pin 2. Clock monitor reset 3. COP (computer operating properly) watchdog reset 4. Unimplemented instruction trap 5. Software interrupt instruction (SWI) 6. XIRQ signal (if X bit in CCR = 0) MC68HC812A4 -- Rev. 3.0 70 Resets and Interrupts Advance Information MOTOROLA Resets and Interrupts Maskable Interrupts 4.4 Maskable Interrupts Maskable interrupt sources include on-chip peripheral systems and external interrupt service requests. Interrupts from these sources are recognized when the global interrupt mask bit (I) in the CCR is cleared. The default state of the I bit out of reset is 1, but it can be written at any time. Interrupt sources are prioritized by default but any one maskable interrupt source may be assigned the highest priority by means of the HPRIO register. The relative priorities of the other sources remain the same. An interrupt that is assigned highest priority is still subject to global masking by the I bit in the CCR or by any associated local bits. Interrupt vectors are not affected by priority assignment. HPRIO can only be written while the I bit is set (interrupts inhibited). Table 4-1 lists interrupt sources and vectors in default order of priority. Table 4-1. Interrupt Vector Map Vector Address Exception Source Flag -- -- -- -- -- -- -- RTIF C0F C1F C2F C3F C4F Local Enable None CME, FCME COP rate selected None None None IRQEN, KWIED7-0 RTIE C0I C1I C2I C3I C4I CCR HPRIO Value Mask to Elevate None None None None None X bit I bit I bit I bit I bit I bit I bit I bit -- -- -- -- -- -- $F2 $F0 $EE $EC $EA $E8 $E6 $FFFE, $FFFF Power-on reset $FFFC, $FFFD COP clock monitor reset $FFFA, $FFFB COP reset $FFF8, $FFF9 Unimplemented instruction trap $FFF6, $FFF7 SWI instruction $FFF4, $FFF5 XIRQ pin $FFF2, $FFF3 IRQ pin or key wakeup D $FFF0, $FFF1 Real-time interrupt $FFEE, $FFEF Timer channel 0 $FFEC, $FFED Timer channel 1 $FFEA, $FFEB Timer channel 2 $FFE8, $FFE9 Timer channel 3 $FFE6, $FFE7 Timer channel 4 Advance Information MOTOROLA Resets and Interrupts MC68HC812A4 -- Rev. 3.0 71 Resets and Interrupts Table 4-1. Interrupt Vector Map (Continued) Vector Address Exception Source Flag C5F C6F C7F TOF PAOVF PAIF SPIF MODF TDRE TC RDRF OR IDLE TDRE TC RDRF OR IDLE ASCIF -- -- -- Local Enable C5I C6I C7I TOI PAOVI PAI SPI0E TIE TCIE RIE RIE ILIE TIE TCIE RIE RIE ILIE ASCIE KWIEJ7-0 KWIEH7-0 -- CCR HPRIO Value Mask to Elevate I bit I bit I bit I bit I bit I bit I bit $E4 $E2 $E0 $DE $DC $DA $D8 $FFE4, $FFE5 Timer channel 5 $FFE2, $FFE3 Timer channel 6 $FFE0, $FFE1 Timer channel 7 $FFDE, $FFDF Timer overflow $FFDC, $FFDD Pulse accumulator overflow $FFDA, $FFDB Pulse accumulator input edge $FFD8, $FFD9 SPI serial transfer complete Mode fault SCI0 transmit data register empty SCI0 transmission complete $FFD6, $FFD7 SCI0 receive data register full SCI0 receiver overrun SCI0 receiver idle SCI1 transmit data register empty SCI1 transmission complete $FFD4, $FFD5 SCI1 receive data register full SCI1 receiver overrun SCI1 receiver idle $FFD2, $FFD3 ATD $FFD0, $FFD1 Key wakeup J (stop wakeup) $FFCE, $FFCF Key wakeup H (stop wakeup) $FF80-$FFCD Reserved I bit $D6 I bit $D4 I bit I bit I bit I bit $D2 $D0 $CE $80-$CC MC68HC812A4 -- Rev. 3.0 72 Resets and Interrupts Advance Information MOTOROLA Resets and Interrupts Interrupt Registers 4.5 Interrupt Registers This section describes the interrupt registers. 4.5.1 Interrupt Control Register Address: $001E Bit 7 Read: IRQE Write: Reset: 0 1 1 0 0 0 0 0 IRQEN DLY 6 5 4 0 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 4-1. Interrupt Control Register (INTCR) Read: Anytime Write: Varies from bit to bit IRQE -- IRQ Edge-Sensitive-Only Bit IRQE can be written once in normal modes. In special modes, IRQE can be written anytime, but the first write is ignored. 1 = IRQ responds only to falling edges. 0 = IRQ pin responds to low levels. IRQEN -- IRQ Enable Bit IRQEN can be written anytime in all modes. The IRQ pin has an internal pullup. 1 = IRQ pin and key wakeup D connected to interrupt logic 0 = IRQ pin and key wakeup D disconnected from interrupt logic DLY -- Oscillator Startup Delay on Exit from Stop Mode Bit DLY can be written once in normal modes. In special modes, DLY can be written anytime. The delay time of about 4096 cycles is based on the M-clock rate chosen. 1 = Stabilization delay on exit from stop mode 0 = No stabilization delay on exit from stop mode Advance Information MOTOROLA Resets and Interrupts MC68HC812A4 -- Rev. 3.0 73 Resets and Interrupts 4.5.2 Highest Priority I Interrupt Register Address: $001F Bit 7 Read: Write: Reset: 1 1 1 1 0 0 1 0 1 6 1 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 5 4 3 2 1 Bit 0 0 = Unimplemented Figure 4-2. Highest Priority I Interrupt Register (HPRIO) Read: Anytime Write: Only if I mask in CCR = 1 (interrupts inhibited) To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO register. For example, writing $F0 to HPRIO assigns highest maskable interrupt priority to the real-time interrupt timer ($FFF0). If an unimplemented vector address or a non-I-masked vector address (a value higher than $F2) is written, then IRQ is the default highest priority interrupt. 4.6 Resets There are five possible sources of reset. Power-on reset (POR), external reset on the RESET pin, and reset from the alternate reset pin, ARST, share the normal reset vector. The computer operating properly (COP) reset and the clock monitor reset each has a vector. Entry into reset is asynchronous and does not require a clock but the MCU cannot sequence out of reset without a system clock. 4.6.1 Power-On Reset A positive transition on VDD causes a power-on reset (POR). An external voltage level detector, or other external reset circuits, are the usual source of reset in a system. The POR circuit only initializes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops. MC68HC812A4 -- Rev. 3.0 74 Resets and Interrupts Advance Information MOTOROLA Resets and Interrupts Effects of Reset 4.6.2 External Reset The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than eight E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for about 16 E-clock cycles, then released. Eight E-clock cycles later, it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor. To prevent a COP or clock monitor reset from being detected during an external reset, hold the reset pin low for at least 32 cycles. An external RC power-up delay circuit on the reset pin is not recommended since circuit charge time can cause the MCU to misinterpret the type of reset that has occurred. 4.6.3 COP Reset The MCU includes a computer operating properly (COP) system to help protect against software failures. When COP is enabled, software must write $55 and $AA (in this order) to the COPRST register to keep a watchdog timer from timing out. Other instructions may be executed between these writes. A write of any value other than $55 or $AA or software failing to execute the sequence properly causes a COP reset to occur. 4.6.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 4.7 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known startup states, as follows. Advance Information MOTOROLA Resets and Interrupts MC68HC812A4 -- Rev. 3.0 75 Resets and Interrupts 4.7.1 Operating Mode and Memory Map The states of the BGND, MODA, and MODB pins during reset determine the operating mode and default memory mapping. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the mode-select inputs at the rising edge of reset. Operating mode and default maps can subsequently be changed according to strictly defined rules. 4.7.2 Clock and Watchdog Control Logic Reset enables the COP watchdog with the CR2-CR0 bits set for the longest timeout period. The clock monitor is disabled. The RTIF flag is cleared and automatic hardware interrupts are masked. The rate control bits are cleared, and must be initialized before the RTI system is used. The DLY control bit is set to specify an oscillator startup delay upon recovery from stop mode. 4.7.3 Interrupts Reset initializes the HPRIO register with the value $F2, causing the IRQ pin to have the highest I bit interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR systems). However, the I and X bits in the CCR are set, masking IRQ and XIRQ interrupt requests. 4.7.4 Parallel I/O If the MCU comes out of reset in an expanded mode, port A and port B are the address bus. Port C and port D are the data bus. In narrow mode, port C alone is the data bus. Port E pins are normally used to control the external bus. The PEAR register affects port E pin operation. If the MCU comes out of reset in a single-chip mode, all ports are configured as general-purpose, high-impedance inputs except in normal narrow expanded mode (NNE). In NNE, PE3 is configured as an output driven high. In expanded modes, PF5 is an active chip-select. MC68HC812A4 -- Rev. 3.0 76 Resets and Interrupts Advance Information MOTOROLA Resets and Interrupts Interrupt Recognition 4.7.5 Central Processor Unit After reset, the CPU fetches a vector from the appropriate address and begins executing instructions. The stack pointer and other CPU registers are indeterminate immediately after reset. The CCR X and I interrupt mask bits are set to mask any interrupt requests. The S bit is also set to inhibit the STOP instruction. 4.7.6 Memory After reset, the internal register block is located at $0000-$01FF and RAM is at $0800-$0BFF. EEPROM is located at $1000-$1FFF in expanded modes and at $F000-$FFFF in single-chip modes. 4.7.7 Other Resources The timer, serial communications interface (SCI), serial peripheral interface (SPI), and analog-to-digital converter (ATD) are off after reset. 4.8 Interrupt Recognition Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared. When an interrupt request is recognized, the CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the instruction. Some of the longer instructions can be interrupted and resume normally after servicing the interrupt. When the CPU begins to service an interrupt request, it: * * * Clears the instruction queue Calculates the return address Stacks the return address and the contents of the CPU registers as shown in Table 4-2 Advance Information MOTOROLA Resets and Interrupts MC68HC812A4 -- Rev. 3.0 77 Resets and Interrupts Table 4-2. Stacking Order on Entry to Interrupts Memory Location SP - 2 SP - 4 SP - 6 SP - 8 SP - 9 Stacked Values RTNH : RTNL YH : YL XH : XL B:A CCR After stacking the CCR, the CPU: * * * * Sets the I bit to prevent other interrupts from disrupting the interrupt service routine Sets the X bit if an XIRQ interrupt request is pending Fetches the interrupt vector for the highest-priority request that was pending at the beginning of the interrupt sequence Begins execution of the interrupt service routine at the location pointed to by the vector If no other interrupt request is pending at the end of the interrupt service routine, an RTI instruction recovers the stacked values. Program execution resumes program at the return address. If another interrupt request is pending at the end of an interrupt service routine, the RTI instruction recovers the stacked values. However, the CPU then: * * * Adjusts the stack pointer to point again at the stacked CCR location, SP - 9 Fetches the vector of the pending interrupt Begins execution of the interrupt service routine at the location pointed to by the vector MC68HC812A4 -- Rev. 3.0 78 Resets and Interrupts Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 5. Operating Modes and Resource Mapping 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.3.1 Normal Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.3.1.1 Normal Expanded Wide Mode . . . . . . . . . . . . . . . . . . . . .81 5.3.1.2 Normal Expanded Narrow Mode . . . . . . . . . . . . . . . . . . .81 5.3.1.3 Normal Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . .81 5.3.2 Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.3.2.1 Special Expanded Wide Mode . . . . . . . . . . . . . . . . . . . . .82 5.3.2.2 Special Expanded Narrow Mode . . . . . . . . . . . . . . . . . . .82 5.3.2.3 Special Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . .82 5.3.2.4 Special Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . .82 5.3.3 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.4 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.5 Mode and Resource Mapping Registers . . . . . . . . . . . . . . . . .85 5.5.1 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.5.2 Register Initialization Register . . . . . . . . . . . . . . . . . . . . . . .87 5.5.3 RAM Initialization Register . . . . . . . . . . . . . . . . . . . . . . . . . .88 5.5.4 EEPROM Initialization Register . . . . . . . . . . . . . . . . . . . . . .88 5.5.5 Miscellaneous Mapping Control Register . . . . . . . . . . . . . . .89 5.6 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 5.2 Introduction The MCU can operate in eight different modes. Each mode has a different default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. Advance Information MOTOROLA Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 79 Operating Modes and Resource Mapping 5.3 Operating Modes The states of the BKGD, MODB, and MODA pins during reset determine the operating mode after reset. The SMODN, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the BKGD, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. Table 5-1. Mode Selection BKGD MODB MODA 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Mode Special single-chip Special expanded narrow Special peripheral Special expanded wide Normal single chip Normal expanded narrow Reserved (forced to peripheral) Normal expanded wide Port A Port B Port C Port D G.P.(1) I/O G.P. I/O G.P. I/O ADDR ADDR ADDR G.P. I/O ADDR -- ADDR DATA DATA DATA G.P. I/O DATA DATA G.P. I/O G.P. I/O DATA -- DATA G.P. I/O -- DATA 1. G.P. = General purpose The two basic types of operating modes are: * * Normal modes -- Some registers and bits are protected against accidental changes. Special modes -- Protected control registers and bits are allowed greater access for special purposes such as testing and emulation. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. MC68HC812A4 -- Rev. 3.0 80 Operating Modes and Resource Mapping Advance Information MOTOROLA Operating Modes and Resource Mapping Operating Modes 5.3.1 Normal Operating Modes These modes provide three operating configurations. Background debugging is available in all three modes, but must first be enabled for some operations by means of a BDM command. BDM can then be made active by another BDM command. 5.3.1.1 Normal Expanded Wide Mode The 16-bit external address bus uses port A for the high byte and port B for the low byte. The 16-bit external data bus uses port C for the high byte and port D for the low byte. 5.3.1.2 Normal Expanded Narrow Mode The 16-bit external address bus uses port A for the high byte and port B for the low byte. The 8-bit external data bus uses port C. In this mode, 16-bit data is presented high byte first, followed by the low byte. The address is automatically incremented on the second cycle. 5.3.1.3 Normal Single-Chip Mode There are no external buses in normal single-chip mode. The MCU operates as a stand-alone device and all program and data resources are on-chip. Port pins can be used for general-purpose I/O (input/output). Advance Information MOTOROLA Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 81 Operating Modes and Resource Mapping 5.3.2 Special Operating Modes Special operating modes are commonly used in factory testing and system development. 5.3.2.1 Special Expanded Wide Mode This mode is for emulation of normal expanded wide mode and emulation of normal single-chip mode with a 16-bit bus. The bus-control pins of port E are all configured for their bus-control output functions rather than general-purpose I/O. 5.3.2.2 Special Expanded Narrow Mode This mode is for emulation of normal expanded narrow mode. External 16-bit data is handled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. Internal operations continue to use full 16-bit data paths. For development purposes, port D can be made available for visibility of 16-bit internal accesses by setting the EMD and IVIS control bits. 5.3.2.3 Special Single-Chip Mode This mode can be used to force the MCU to active BDM mode to allow system debug through the BKGD pin. There are no external address and data buses in this mode. The MCU operates as a stand-alone device and all program and data space are on-chip. External port pins can be used for general-purpose I/O. 5.3.2.4 Special Peripheral Mode The CPU is not active in this mode. An external master can control on-chip peripherals for testing purposes. It is not possible to change to or from this mode without going through reset. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both modes. MC68HC812A4 -- Rev. 3.0 82 Operating Modes and Resource Mapping Advance Information MOTOROLA Operating Modes and Resource Mapping Internal Resource Mapping 5.3.3 Background Debug Mode Background debug mode (BDM) is an auxiliary operating mode that is used for system development. BDM is implemented in on-chip hardware and provides a full set of debug operations. Some BDM commands can be executed while the CPU is operating normally. Other BDM commands are firmware based and require the BDM firmware to be enabled and active for execution. In special single-chip mode, BDM is enabled and active immediately out of reset. BDM is available in all other operating modes, but must be enabled before it can be activated. BDM should not be used in special peripheral mode because of potential bus conflicts. Once enabled, background mode can be made active by a serial command sent via the BKGD pin or execution of a CPU12 BGND instruction. While background mode is active, the CPU can interpret special debugging commands, and read and write CPU registers, peripheral registers, and locations in memory. While BDM is active, the CPU executes code located in a small on-chip ROM mapped to addresses $FF20 to $FFFF, and BDM control registers are accessible at addresses $FF00 to $FF06. The BDM ROM replaces the regular system vectors while BDM is active. While BDM is active, the user memory from $FF00 to $FFFF is not in the map except through serial BDM commands. 5.4 Internal Resource Mapping The internal register block, RAM, and EEPROM have default locations within the 64-Kbyte standard address space but may be reassigned to other locations during program execution by setting bits in mapping registers INITRG, INITRM, and INITEE. During normal operating modes, these registers can be written once. It is advisable to explicitly establish these resource locations during the initialization phase of program execution, even if default values are chosen, to protect the registers from inadvertent modification later. Advance Information MOTOROLA Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 83 Operating Modes and Resource Mapping Writes to the mapping registers go into effect between the cycle that follows the write and the cycle after that. To assure that there are no unintended operations, a write to one of these registers should be followed with a NOP (no operation) instruction. If conflicts occur when mapping resources, the register block takes precedence over the other resources; RAM or EEPROM addresses occupied by the register block are not available for storage. When active, BDM ROM takes precedence over other resources although a conflict between BDM ROM and register space is not possible. Table 5-2 shows resource mapping precedence. All address space not used by internal resources is external memory by default. The memory expansion module manages three memory overlay windows: 1. Program 2. Data 3. One extra page overlay The sizes and locations of the program and data overlay windows are fixed. One of two locations can be selected for the extra page (EPAGE). Table 5-2. Mapping Precedence Precedence 1 2 3 4 5 Resource BDM ROM (if active) Register space RAM EEPROM External memory MC68HC812A4 -- Rev. 3.0 84 Operating Modes and Resource Mapping Advance Information MOTOROLA Operating Modes and Resource Mapping Mode and Resource Mapping Registers 5.5 Mode and Resource Mapping Registers This section describes the mode and resource mapping registers. 5.5.1 Mode Register MODE controls the MCU operating mode and various configuration options. This register is not in the map in peripheral mode. Address: $000B Bit 7 Read: SMODN Write: Reset States Special single-chip: Special expanded narrow: Peripheral: Special expanded wide: Normal single-chip: Normal expanded narrow: Normal expanded wide: 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 MODB MODA ESTR IVIS 0 EMD EME 6 5 4 3 2 1 Bit 0 Figure 5-1. Mode Register (MODE) Read: Anytime Write: Varies from bit to bit SMODN, MODB, and MODA -- Mode Select Special, B, and A Bits These bits show the current operating mode and reflect the status of the BKGD, MODB, and MODA input pins at the rising edge of reset. SMODN can be written only if SMODN = 0 (in special modes) but the first write is ignored. MODB and MODA may be written once if SMODN = 1; anytime if SMODN = 0, except that special peripheral and reserved modes cannot be selected. Advance Information MOTOROLA Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 85 Operating Modes and Resource Mapping ESTR -- E-Clock Stretch Enable Bit ESTR determines if the E-clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. 1 = E stretches high during external access cycles and low during non-visible internal accesses. 0 = E never stretches (always free running). Normal modes: Write once Special modes: Write anytime IVIS -- Internal Visibility Bit IVIS determines whether internal ADDR, DATA, R/W, and LSTRB signals can be seen on the external bus during accesses to internal locations. If this bit is set in special narrow mode and EMD = 1 when an internal access occurs, the data appears wide on port C and port D. This allows for emulation. Visibility is not available when the part is operating in a single-chip mode. 1 = Internal bus operations are visible on external bus. 0 = Internal bus operations are not visible on external bus. Normal modes: Write once Special modes: Write anytime except the first time EMD -- Emulate Port D Bit This bit only has meaning in special expanded narrow mode. In expanded wide modes and special peripheral mode, PORTD, DDRD, KWIED, and KWIFD are removed from the memory map regardless of the state of this bit. In single-chip modes and normal expanded narrow mode, PORTD, DDRD, KWIED, and KWIFD are in the memory map regardless of the state of this bit. 1 = If in special expanded narrow mode, PORTD, DDRD, KWIED, and KWIFD are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. 0 = PORTD, DDRD, KWIED, and KWIFD are in the memory map. Normal modes: Write once Special modes: Write anytime except the first time MC68HC812A4 -- Rev. 3.0 86 Operating Modes and Resource Mapping Advance Information MOTOROLA Operating Modes and Resource Mapping Mode and Resource Mapping Registers EME -- Emulate Port E Bit In single-chip mode, PORTE and DDRE are always in the map regardless of the state of this bit. 1 = If in an expanded mode, PORTE and DDRE are removed from the internal memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. 0 = PORTE and DDRE in the memory map Normal modes: Write once Special modes: Write anytime except the first time 5.5.2 Register Initialization Register After reset, the 512-byte register block resides at location $0000 but can be reassigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal registers is controlled by five bits in the INITRG register. The register block occupies the first 512 bytes of the 2-Kbyte block. Address: $0011 Bit 7 Read: REG15 Write: Reset: 0 0 0 0 0 0 0 0 REG14 REG13 REG12 REG11 0 0 0 6 5 4 3 2 1 Bit 0 Figure 5-2. Register Initialization Register (INITRG) Read: Anytime Write: Once in normal modes; anytime in special modes REG15-REG11 -- Register Position Bits These bits specify the upper five bits of the 16-bit register address. Advance Information MOTOROLA Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 87 Operating Modes and Resource Mapping 5.5.3 RAM Initialization Register After reset, addresses of the 1-Kbyte RAM array begin at location $0800 but can be assigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal RAM is controlled by five bits in the INITRM register. The RAM array occupies the last 1 Kbyte of the 2-Kbyte block. Address: $0010 Bit 7 Read: RAM15 Write: Reset: 0 0 0 0 1 0 0 0 RAM14 RAM13 RAM12 RAM11 0 0 0 6 5 4 3 2 1 Bit 0 Figure 5-3. RAM Initialization Register (INITRM) Read: Anytime Write: Once in normal modes; anytime in special modes RAM15-RAM11 -- RAM Position Bits These bits specify the upper five bits of the 16-bit RAM address. 5.5.4 EEPROM Initialization Register The MCU has 4 Kbytes of EEPROM which is activated by the EEON bit in the INITEE register. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset, EEPROM address space begins at location $1000 but can be mapped to any 4-Kbyte boundary within the standard 64-Kbyte address space. MC68HC812A4 -- Rev. 3.0 88 Operating Modes and Resource Mapping Advance Information MOTOROLA Operating Modes and Resource Mapping Mode and Resource Mapping Registers Address: $0012 Bit 7 Read: EE15 Write: Reset: Expanded and peripheral: Single-chip: 0 1 0 1 0 1 1 1 0 0 0 0 0 0 1 1 EE14 EE13 EE12 0 0 0 EEON 6 5 4 3 2 1 Bit 0 Figure 5-4. EEPROM Initialization Register (INITEE) Read: Anytime Write: Varies from bit to bit EE15-EE12 -- EEPROM Position Bits These bits specify the upper four bits of the 16-bit EEPROM address. Normal modes: Write once Special modes: Write anytime EEON -- EEPROM On Bit EEON enables the on-chip EEPROM. EEON is forced to 1 in single-chip modes. Write anytime 1 = EEPROM at address selected by EE15-EE12 0 = EEPROM removed from memory map 5.5.5 Miscellaneous Mapping Control Register Additional mapping controls are available that can be used in conjunction with memory expansion and chip selects. To use memory expansion, the part must be operated in one of the expanded modes. Sections of the standard 64-Kbyte memory map have memory expansion windows which allow more than 64 Kbytes to be addressed externally. Memory expansion consists of three memory expansion windows and six address lines in addition to the existing standard 16 address lines. The memory expansion function reuses as Advance Information MOTOROLA Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 89 Operating Modes and Resource Mapping many as six of the standard 16 address lines. Usage of chip selects identifies the source of the internal address. All of the memory expansion windows have a fixed size and two of them have a fixed address location. The third has two selectable address locations. Address: $0013 Bit 7 Read: EWDIR Write: Reset: 0 0 0 0 0 0 0 0 NDRC 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 5-5. Miscellaneous Mapping Control Register (MISC) Read: Anytime Write: Once in normal modes; anytime in special modes EWDIR -- Extra Window Positioned in Direct Space Bit This bit is only valid in expanded modes. If the EWEN bit in the WINDEF register is cleared, then this bit has no meaning or effect. 1 = If EWEN is set, then a 1 in this bit places the EPAGE at $0000-$03FF. 0 = If EWEN is set, then a 0 in this bit places the EPAGE at $0400-$07FF. NDRC -- Narrow Data Bus for Register Chip-Select Space Bit This function requires at least one of the chip selects CS3-CS0 to be enabled. It effects the external 512-byte memory space. 1 = Makes the register-following chip-selects (2, 1, 0, and sometimes 3) active space (512-byte block) act the same as an 8-bit only external data bus. Data only goes through port C externally. This allows 8-bit and 16-bit external memory devices to be mixed in a system. 0 = Makes the register-following chip-select active space act as a full 16-bit data bus. In the narrow (8-bit) mode, NDRC has no effect. MC68HC812A4 -- Rev. 3.0 90 Operating Modes and Resource Mapping Advance Information MOTOROLA Operating Modes and Resource Mapping Memory Map 5.6 Memory Map Figure 5-6 illustrates the memory map for each mode of operation immediately after reset. $0000 EXT $0800 EXT $1000 $2000 $0000 $01FF $0800 $0BFF $1000 REGISTERS MAPPABLE TO ANY 2-K SPACE RAM MAPPABLE TO ANY 2-K SPACE EEPROM MAPPABLE TO ANY 4-K SPACE $1FFF EXT $F000 $F000 $FF00 $FFC0 $FFFF $FF00 BDM IF ACTIVE VECTORS VECTORS VECTORS EEPROM SINGLE-CHIP MODES $FFFF $FFFF EXPANDED SINGLE-CHIP NORMAL SINGLE-CHIP SPECIAL Figure 5-6. Memory Map Advance Information MOTOROLA Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 91 Operating Modes and Resource Mapping MC68HC812A4 -- Rev. 3.0 92 Operating Modes and Resource Mapping Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 6. Bus Control and Input/Output (I/O) 6.1 Contents 6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Detecting Access Type from External Signals . . . . . . . . . . . . .94 6.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 6.4.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 6.4.2 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .96 6.4.3 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 6.4.4 Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .97 6.4.5 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 6.4.6 Port C Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .99 6.4.7 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 6.4.8 Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . .101 6.4.9 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 6.4.10 Port E Data Direction Register . . . . . . . . . . . . . . . . . . . . . .103 6.4.11 Port E Assignment Register . . . . . . . . . . . . . . . . . . . . . . . .104 6.4.12 Pullup Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .107 6.4.13 Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . .108 6.2 Introduction Internally the MCU has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8-bit or 16-bit data. Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 93 Bus Control and Input/Output (I/O) 6.3 Detecting Access Type from External Signals The external signals LSTRB, R/W, and A0 can be used to determine the type of bus access that is taking place. Accesses to the internal RAM module are the only type of access that produce LSTRB = A0 = 1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases, the data for the address that was accessed is on the low half of the data bus and the data for address +1 is on the high half of the data bus. Table 6-1. Access Type versus Bus Control Pins LSTRB 1 0 1 0 0 1 0 1 A0 0 1 0 1 0 1 0 1 R/W 1 1 0 0 1 1 0 0 Type of Access 8-bit read of an even address 8-bit read of an odd address 8-bit write of an even address 8-bit write of an odd address 16-bit read of an even address 16-bit read of an odd address (low/high data swapped) 16-bit write to an even address 16-bit write to an even address (low/high data swapped) MC68HC812A4 -- Rev. 3.0 94 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers 6.4 Registers Not all registers are visible in the memory map under certain conditions. In special peripheral mode, the first 16 registers associated with bus expansion are removed from the memory map. In expanded modes, some or all of port A, port B, port C, port D, and port E are used for expansion buses and control signals. To allow emulation of the single-chip functions of these ports, some of these registers must be rebuilt in an external port replacement unit. In any expanded mode, port A, port B, and port C are used for address and data lines so registers for these ports, as well as the data direction registers for these ports, are removed from the on-chip memory map and become external accesses. Port D and its associated data direction register may be removed from the on-chip map when port D is needed for 16-bit data transfers. If the MCU is in an expanded wide mode, port C and port D are used for 16-bit data and the associated port and data direction registers become external accesses. When the MCU is in expanded narrow mode, the external data bus is normally 8 bits. To allow full-speed operation while allowing visibility of internal 16-bit accesses, a 16-bit-wide data path is required. The emulate port D (EMD) control bit in the MODE register may be set to allow such 16-bit transfers. In this case of narrow special expanded mode and the EMD bit set, port D and data direction D registers are removed from the on-chip memory map and become external accesses so port D may be rebuilt externally. In any expanded mode, port E pins may be needed for bus control (for instance, ECLK and R/W). To regain the single-chip functions of port E, the emulate port E (EME) control bit in the MODE register may be set. In this special case of expanded mode and EME set, PORTE and DDRE registers are removed from the on-chip memory map and become external accesses so port E may be rebuilt externally. Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 95 Bus Control and Input/Output (I/O) 6.4.1 Port A Data Register Address: $0000 Bit 7 Read: PA7 Write: Reset: 0 0 ADDR14 0 ADDR13 0 ADDR12 0 ADDR11 0 ADDR10 0 ADDR9 0 ADDR8 PA6 PA5 PA4 PA3 PA2 PA1 PA0 6 5 4 3 2 1 Bit 0 Expanded and peripheral: ADDR15 Figure 6-1. Port A Data Register (PORTA) Read: Anytime, if register is in the map Write: Anytime, if register is in the map Bits PA7-PA0 are associated with addresses ADDR15-ADDR8 respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O. DDRA determines the primary direction of each pin. This register is not in the on-chip map in expanded and peripheral modes. 6.4.2 Port A Data Direction Register Address: $0002 Bit 7 Read: DDRA7 Write: Reset: 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 6 5 4 3 2 1 Bit 0 Figure 6-2. Port A Data Direction Register (DDRA) Read: Anytime, if register is in the map Write: Anytime, if register is in the map This register determines the primary direction for each port A pin when functioning as a general-purpose I/O port. DDRA is not in the on-chip map in expanded and peripheral modes. 1 = Associated pin is an output. 0 = Associated pin is a high-impedance input. MC68HC812A4 -- Rev. 3.0 96 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers 6.4.3 Port B Data Register Address: $0001 Bit 7 Read: PB7 Write: Reset: Expanded and peripheral: 0 ADDR7 0 ADDR6 0 ADDR5 0 ADDR4 0 ADDR3 0 ADDR2 0 ADDR1 0 ADDR0 PB6 PB5 PB4 PB3 PB2 PB1 PB0 6 5 4 3 2 1 Bit 0 Figure 6-3. Port B Data Register (PORTB) Read: Anytime, if register is in the map Write: Anytime, if register is in the map Bits PB7-PB0 correspond to address lines ADDR7-ADDR0. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O. DDRB determines the primary direction of each pin. This register is not in the on-chip map in expanded and peripheral modes. 6.4.4 Port B Data Direction Register Address: $0003 Bit 7 Read: DDRB7 Write: Reset: 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 6 5 4 3 2 1 Bit 0 Figure 6-4. Port B Data Direction Register (DDRB) Read: Anytime, if register is in the map Write: Anytime, if register is in the map This register determines the primary direction for each port B pin when functioning as a general-purpose I/O port. DDRB is not in the on-chip map in expanded and peripheral modes. 1 = Associated pin is an output. 0 = Associated pin is a high-impedance input. Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 97 Bus Control and Input/Output (I/O) 6.4.5 Port C Data Register Address: $0004 Bit 7 Read: PC7 Write: Reset: 0 0 DATA14 0 DATA13 0 DATA12 0 DATA11 0 DATA10 0 DATA9 0 DATA8 DATA8/0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 6 5 4 3 2 1 Bit 0 Expanded wide and peripheral: DATA15 Expanded narrow: DATA15/7 DATA14/6 DATA13/5 DATA12/4 DATA11/3 DATA10/2 DATA9/1 Figure 6-5. Port C Data Register (PORTC) Read: Anytime, if register is in the map Write: Anytime, if register is in the map Bits PC7-PC0 correspond to data lines DATA15-DATA8. When this port is not used for external data such as in single-chip mode, these pins can be used as general-purpose I/O. DDRC determines the primary direction for each pin. In narrow expanded modes, DATA15-DATA8 and DATA7-DATA0 are multiplexed into the MCU through port C pins on successive cycles. This register is not in the on-chip map in expanded and peripheral modes. When the MCU is operating in special expanded narrow mode and port C and port D are being used for internal visibility, internal accesses produce full 16-bit information with DATA15-DATA8 on port C and DATA7-DATA0 on port D. This allows the MCU to operate at full speed while making 16-bit access information available to external development equipment in a single cycle. In this narrow mode, normal 16-bit accesses to external memory get split into two successive 8-bit accesses on port C alone. MC68HC812A4 -- Rev. 3.0 98 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers 6.4.6 Port C Data Direction Register Address: $0006 Bit 7 Read: DDRC7 Write: Reset: 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 6 5 4 3 2 1 Bit 0 Figure 6-6. Port C Data Direction Register (DDRC) Read: Anytime, if register is in the map Write: Anytime, if register is in the map DDRC is not in the on-chip map in expanded and peripheral modes. This register determines the primary direction for each port C pin when functioning as a general-purpose I/O port. 1 = Associated pin is an output. 0 = Associated pin is a high-impedance input. Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 99 Bus Control and Input/Output (I/O) 6.4.7 Port D Data Register Address: $0005 Bit 7 Read: PD7 Write: Reset: Expanded wide and peripheral: Alternate pin function: 0 DATA7 KWD7 0 DATA6 KWD6 0 DATA5 KWD5 0 DATA4 KWD4 0 DATA3 KWD3 0 DATA2 KWD2 0 DATA1 KWD1 0 DATA0 KWD0 PD6 PD5 PD4 PD3 PD2 PD1 PD0 6 5 4 3 2 1 Bit 0 Figure 6-7. Port D Data Register (PORTD) Read: Anytime, if register is in the map Write: Anytime, if register is in the map Bits PD7-PD0 correspond to data lines DATA7-DATA0. When port D is not used for external data, such as in single-chip mode, these pins can be used as general-purpose I/O or key wakeup signals. DDRD determines the primary direction of each port D pin. In special expanded narrow mode, the external data bus is normally limited to eight bits on port C, but the emulate port D bit (EMD) in the MODE register can be set to allow port C and port D to be used together to provide single-cycle visibility of internal 16-bit accesses for debugging purposes. If the mode is special narrow expanded and EMD is set, port D is configured for DATA7-DATA0 of visible internal accesses and normal 16-bit external accesses are split into two adjacent 8-bit accesses through port C. This allows connection of a single 8-bit external program memory. This register is not in the on-chip map in wide expanded and peripheral modes. Also, in special narrow expanded mode, the function of this port is determined by the EMD control bit. If EMD is set, this register is not in the on-chip map and port D is used for DATA7-DATA0 of visible internal accesses. If EMD is clear, this port serves as general-purpose I/O or key wakeup signals. MC68HC812A4 -- Rev. 3.0 100 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers 6.4.8 Port D Data Direction Register Address: $0007 Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 6-8. Port D Data Direction Register (DDRD) Read: Anytime, if register is in the map Write: Anytime, if register is in the map When port D is operating as a general-purpose I/O port, this register determines the primary direction for each port D pin. 1 = Associated pin is an output. 0 = Associated pin is a high-impedance input. This register is not in the map in wide expanded and peripheral modes. Also, in special narrow expanded mode, the function of this port is determined by the EMD control bit. If EMD is set, this register is not in the on-chip map and port D is used for DATA7-DATA0 of visible internal accesses. If EMD is clear, this port serves as general-purpose I/O or key wakeup signals. Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 101 Bus Control and Input/Output (I/O) 6.4.9 Port E Data Register Address: $0008 Bit 7 Read: PE7 Write: Reset: Normal narrow expanded: All other modes: Alternate pin function: 0 0 ARST 0 0 0 0 Unaffected by reset 0 0 ECLK 1 0 LSTRB 0 0 R/W 0 0 IRQ 0 0 XIRQ PE6 PE5 PE4 PE3 PE2 PE1 PE0 6 5 4 3 2 1 Bit 0 MODB or MODA or IPIPE1 IPIPE0 Figure 6-9. Port E Data Register (PORTE) Read: Anytime, if register is in the map Write: Anytime, if register is in the map This register is associated with external bus control signals and interrupt inputs including auxiliary reset (ARST), mode select (MODB/IPIPE1, MODA/IPIPE0), E-clock, size (LSTRB), read/write (R/W), IRQ, and XIRQ. When the associated pin is not used for one of these specific functions, the pin can be used as general-purpose I/O. The port E assignment register (PEAR) selects the function of each pin. DDRE determines the primary direction of each port E pin when configured to be general-purpose I/O. Some of these pins have software selectable pullups (LSTRB, R/W, and XIRQ). A single control bit enables the pullups for all these pins which are configured as inputs. IRQ always has a pullup. PE7 can be selected as a high-true auxiliary reset input. This register is not in the map in peripheral mode or expanded modes when the EME bit is set. MC68HC812A4 -- Rev. 3.0 102 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers 6.4.10 Port E Data Direction Register Address: $0009 Bit 7 Read: DDRE7 Write: Reset: Normal narrow expanded: All other modes: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 6 5 4 3 2 1 Bit 0 Figure 6-10. Port E Data Direction Register (DDRE) Read: Anytime, if register is in the map Write: Anytime, if register is in the map This register determines the primary direction for each port E pin configured as general-purpose I/O. 1 = Associated pin is an output. 0 = Associated pin is a high-impedance input. PE1 and PE0 are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can be read regardless of whether the alternate interrupt functions are enabled. This register is not in the map in peripheral mode and expanded modes while the EME control bit is set. Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 103 Bus Control and Input/Output (I/O) 6.4.11 Port E Assignment Register Address: $000A Bit 7 Read: Write: Reset: Special single-chip: Special expanded narrow: Peripheral: Special expanded wide: Normal single-chip Normal expanded narrow: Normal expanded wide: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARSIE 6 PLLTE 5 PIPOE 4 NECLK 3 LSTRE 2 RDWE 1 0 Bit 0 0 Figure 6-11. Port E Assignment Register (PEAR) Read: Anytime, if register is in the map Write: Varies from bit to bit if register is in the map The PEAR register selects between the general-purpose I/O functions and the alternate bus-control functions of port E. The alternate bus-control functions override the associated DDRE bits. The reset condition of this register depends on the mode of operation. * * * In normal single-chip mode, port E is general-purpose I/O. In special single-chip mode, the E-clock is enabled as a timing reference, and the rest of port E is general-purpose I/O. In normal expanded modes, the E-clock is configured for its alternate bus-control function, and the other bits of port E are general-purpose I/O. The reset vector is located in external memory and the E-clock may be required for this access. If R/W is needed for external writable resources, PEAR can be written during normal expanded modes. In special expanded modes, IPIPE1, IPIPE0, E, R/W, and LSTRB are configured as bus-control signals. * MC68HC812A4 -- Rev. 3.0 104 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers In peripheral mode, the PEAR register is not accessible for reads or writes. However, the PLLTE control bit is cleared to configure PE6 as a test output from the PLL module. ARSIE -- Auxiliary Reset Input Enable Bit Write anytime. 1 = PE7 is a high-true reset input; reset timing is the same as that of the low-true RESET pin. 0 = PE7 is general-purpose I/O. PLLTE -- PLL Testing Enable Bit Normal modes: Write never Special modes: Write anytime except the first time 1 = PE6 is a test signal output from the PLL module (no effect in single-chip or normal expanded modes); PIPOE = 1 overrides this function and forces PE6 to be a pipe status output signal. 0 = PE6 is general-purpose I/O or pipe output. PIPOE -- Pipe Status Signal Output Enable Bit Normal modes: Write once Special modes: Write anytime except the first time 1 = PE6 and PE5 are outputs and indicate the state of the instruction queue; no effect in single-chip modes. 0 = PE6 and PE5 are general-purpose I/O; if PLLTE = 1, PE6 is a test output signal from the PLL module. NECLK -- No External E Clock Bit Normal modes: Write anytime Special modes: Write never In peripheral mode, E is an input; in all other modes, E is an output. 1 = PE4 is a general-purpose I/O pin. 0 = PE4 is the external E-clock pin. To get a free-running E-clock in single-chip modes, use NECLK = 0 and IVIS = 1. A 16-bit write to PEAR:MODE can configure these bits in one operation. Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 105 Bus Control and Input/Output (I/O) LSTRE -- Low Strobe (LSTRB) Enable Bit Normal modes: Write once Special modes: Write anytime except the first time LSTRE has no effect in single-chip or normal expanded narrow modes. 1 = PE3 is configured as the LSTRB bus-control output, except in single-chip or normal expanded narrow modes. 0 = PE3 is a general-purpose I/O pin. LSTRB is for external writes. After reset in normal expanded mode, LSTRB is disabled. If needed, it must be enabled before external writes. External reads do not normally need LSTRB because all 16 data bits can be driven even if the MCU only needs eight bits of data. In normal expanded narrow mode, this pin is reset to an output driving high allowing the pin to be an output while in and immediately after reset. RDWE -- Read/Write Enable Bit Normal modes: Write once Special modes: Write anytime except the first time RDWE has no effect in single-chip modes. 1 = PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a general-purpose I/O pin. 0 = PE2 is a general-purpose I/O pin. R/W is used for external writes. After reset in normal expanded mode, it is disabled. If needed, it must be enabled before any external writes. MC68HC812A4 -- Rev. 3.0 106 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers 6.4.12 Pullup Control Register Address: $000C Bit 7 Read: PUPH Write: Reset: 1 1 1 1 1 1 1 1 PUPG PUPF PUPE PUPD PUC PUPB PUPA 6 5 4 3 2 1 Bit 0 Figure 6-12. Pullup Control Register (PUCR) Read: Anytime, if register is in the map Write: Anytime, if register is in the map This register is not in the map in peripheral mode. These bits select pullup resistors for any pin in the corresponding port that is currently configured as an input. PUPH -- Pullup Port H Enable Bit 1 = Enable pullup devices for all port H input pins 0 = Port H pullups disabled PUPG -- Pullup Port G Enable Bit 1 = Enable pullup devices for all port G input pins 0 = Port G pullups disabled PUPF -- Pullup Port F Enable Bit 1 = Enable pullup devices for all port F input pins 0 = Port F pullups disabled PUPE -- Pullup Port E Enable Bit 1 = Enable pullup devices for port E input pins PE3, PE2, and PE0 0 = Port E pullups on PE3, PE2, and PE0 disabled PUPD -- Pullup Port D Enable Bit 1 = Enable pullup devices for all port D input pins 0 = Port D pullups disabled This bit has no effect if port D is being used as part of the data bus (the pullups are inactive). Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 107 Bus Control and Input/Output (I/O) PUPC -- Pullup Port C Enable Bit 1 = Enable pullup devices for all port C input pins 0 = Port C pullups disabled This bit has no effect if port C is being used as part of the data bus (the pullups are inactive). PUPB -- Pullup Port B Enable Bit 1 = Enable pullup devices for all port B input pins 0 = Port B pullups disabled This bit has no effect if port B is being used as part of the address bus (the pullups are inactive). PUPA -- Pullup Port A Enable Bit 1 = Enable pullup devices for all port A input pins 0 = Port A pullups disabled This bit has no effect if port A is being used as part of the address bus (the pullups are inactive). 6.4.13 Reduced Drive Register Address: $000D Bit 7 Read: RDPJ Write: Reset: 0 0 0 0 0 0 0 0 RDPH RDPG RDPF RDPE PRPD RDPC RDPAB 6 5 4 3 2 1 Bit 0 Figure 6-13. Reduced Drive Register (RDRIV) Read: Anytime, if register is in the map Write: Anytime, in normal modes; never in special modes This register is not in the map in peripheral mode. These bits select reduced drive for the associated port pins. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). The reduced drive function is independent of which function is being used on a particular port. MC68HC812A4 -- Rev. 3.0 108 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Bus Control and Input/Output (I/O) Registers RDPJ -- Reduced Drive of Port J Bit 1 = Reduced drive for all port J output pins 0 = Full drive for all port J output pins RDPH -- Reduced Drive of Port H Bit 1 = Reduced drive for all port H output pins 0 = Full drive for all port H output pins RDPG -- Reduced Drive of Port G Bit 1 = Reduced drive for all port G output pins 0 = Full drive for all port G output pins RDPF -- Reduced Drive of Port F Bit 1 = Reduced drive for all port F output pins 0 = Full drive for all port F output pins RDPE -- Reduced Drive of Port E Bit 1 = Reduced drive for all port E output pins 0 = Full drive for all port E output pins RDPD -- Reduced Drive of Port D Bit 1 = Reduced drive for all port D output pins 0 = Full drive for all port D output pins RDPC -- Reduced Drive of Port C Bit 1 = Reduced drive for all port C output pins 0 = Full drive for all port C output pins RDPAB -- Reduced Drive of Port A and Port B Bit 1 = Reduced drive for all port A and port B output pins 0 = Full drive for all port A and port B output pins Advance Information MOTOROLA Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 109 Bus Control and Input/Output (I/O) MC68HC812A4 -- Rev. 3.0 110 Bus Control and Input/Output (I/O) Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 7. EEPROM 7.1 Contents 7.2 7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 EEPROM Programmer's Model . . . . . . . . . . . . . . . . . . . . . . .112 7.4 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .114 7.4.1 EEPROM Module Configuration Register . . . . . . . . . . . . .114 7.4.2 EEPROM Block Protect Register . . . . . . . . . . . . . . . . . . . .115 7.4.3 EEPROM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.4.4 EEPROM Programming Register . . . . . . . . . . . . . . . . . . . .117 7.2 Introduction The MC68HC812A4 EEPROM (electrically erasable, programmable, read-only memory) serves as a 4096-byte nonvolatile memory which can be used for frequently accessed static data or as fast access program code. Operating system kernels and standard subroutines would benefit from this feature. The MC68HC812A4 EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words, or misaligned words. Access times are one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. Programming is by byte or aligned word. Attempts to program or erase misaligned words will fail. Only the lower byte will be latched and programmed or erased. Programming and erasing of the user EEPROM can be done in all modes. Advance Information MOTOROLA EEPROM MC68HC812A4 -- Rev. 3.0 111 EEPROM Each EEPROM byte or aligned word must be erased before programming. The EEPROM module supports byte, aligned word, row (32 bytes), or bulk erase, all using the internal charge pump. Bulk erasure of odd and even rows is also possible in test modes; the erased state is $FF. The EEPROM module has hardware interlocks which protect stored data from corruption by accidentally enabling the program/erase voltage. Programming voltage is derived from the internal VDD supply with an internal charge pump. The EEPROM has a minimum program/erase life of 10,000 cycles over the complete operating temperature range. 7.3 EEPROM Programmer's Model The EEPROM module consists of two separately addressable sections. The first is a 4-byte memory mapped control register block used for control, testing and configuration of the EEPROM array. The second section is the EEPROM array itself. At reset, the 4-byte register section starts at address $00F0 and the EEPROM array is located from addresses $1000 to $1FFF (see Figure 7-1). For information on remapping the register block and EEPROM address space, refer to Section 5. Operating Modes and Resource Mapping. Read/write access to the memory array section can be enabled or disabled by the EEON control bit in the INITEE register. This feature allows the access of memory mapped resources that have lower priority than the EEPROM memory array. EEPROM control registers can be accessed and EEPROM locations may be programmed or erased regardless of the state of EEON. Using the normal EEPROG control, it is possible to continue program/erase operations during wait. For lowest power consumption during wait, stop program/erase by turning off EEPGM. MC68HC812A4 -- Rev. 3.0 112 EEPROM Advance Information MOTOROLA EEPROM EEPROM Programmer's Model If the stop mode is entered during programming or erasing, program/erase voltage is automatically turned off and the RC clock (if enabled) is stopped. However, the EEPGM control bit remains set. When stop mode is terminated, the program/erase voltage automatically turns back on if EEPGM is set. At low bus frequencies, the RC clock must be turned on for program/erase. $_000 BPROT6 2 KBYTES BPROT5 1 KBYTE BPROT4 512 BYTES BPROT3 256 BYTES BPROT2 128 BYTES BPROT1 64 BYTES BPROT0 64 BYTES SINGLE-CHIP VECTORS RESERVED 64 BYTES VECTORS 64 BYTES $FF80 $FFBF $FFC0 $FFFF $_800 $_C00 $_E00 $_F00 $_F80 $_FC0 $_FFF Figure 7-1. EEPROM Block Protect Mapping Advance Information MOTOROLA EEPROM MC68HC812A4 -- Rev. 3.0 113 EEPROM 7.4 EEPROM Control Registers This section describes the EEPROM control registers. 7.4.1 EEPROM Module Configuration Register Address: $00F0 Bit 7 Read: 1 Write: Reset: 1 1 1 1 1 1 0 0 1 1 1 1 EESWAI PROTLCK EERC 6 5 4 3 2 1 Bit 0 Figure 7-2. EEPROM Module Configuration Register (EEMCR) Read: Anytime Write: Varies from bit to bit EESWAI -- EEPROM Stops in Wait Mode Bit 0 = Module is not affected during wait mode. 1 = Module ceases to be clocked during wait mode. This bit should be cleared if the wait mode vectors are mapped in the EEPROM array. PROTLCK -- Block Protect Write Lock Bit 0 = Block protect bits and bulk erase protection bit can be written. 1 = Block protect bits are locked. Write once in normal modes (SMODN = 1). Set and clear anytime in special modes (SMODN = 0). EERC -- EEPROM Charge Pump Clock Bit 0 = System clock is used as clock source for the internal charge pump; internal RC oscillator is stopped. 1 = Internal RC oscillator drives the charge pump; RC oscillator is required when the system bus clock is lower than fPROG. Write anytime MC68HC812A4 -- Rev. 3.0 114 EEPROM Advance Information MOTOROLA EEPROM EEPROM Control Registers 7.4.2 EEPROM Block Protect Register Address: $00F1 Bit 7 Read: 1 Write: Reset: 1 1 1 1 1 1 1 1 BPROT6 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 6 5 4 3 2 1 Bit 0 Figure 7-3. EEPROM Block Protect Register (EEPROT) Read: Anytime Write: Anytime if EEPGM = 0 and PROTLCK = 0 This register prevents accidental writes to EEPROM. BPROT6-BPROT0 -- EEPROM Block Protection Bit 0 = Associated EEPROM block can be programmed and erased. 1 = Associated EEPROM block is protected from being programmed and erased. These bits cannot be modified while programming is taking place (EEPGM = 1). Table 7-1. 4-Kbyte EEPROM Block Protection Bit Name BPROT6 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 Block Protected $1000 to $17FF $1800 to $1BFF $1C00 to $1DFF $1E00 to $1EFF $1F00 to $1F7F $1F80 to $1FBF $1FC0 to $1FFF Block Size 2048 bytes 1024 bytes 512 bytes 256 bytes 128 bytes 64 bytes 64 bytes Advance Information MOTOROLA EEPROM MC68HC812A4 -- Rev. 3.0 115 EEPROM 7.4.3 EEPROM Test Register Address: $00F2 Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 EEODD 6 EEVEN 5 MARG 4 EECPD 3 EECPRD 2 0 1 EECPM Bit 0 0 Figure 7-4. EEPROM Test Register (EEPROT) Read: Anytime Write: In special modes only (SMODN = 0) These bits are used for test purposes only. In normal modes, the bits are forced to 0. EEODD -- Odd Row Programming Bit 1 = Bulk program/erase all odd rows 0 = Odd row bulk programming/erasing disabled EEVEN -- Even Row Programming Bit 1 = Bulk program/erase all even rows 0 = Even row bulk programming/erasing disabled MARG -- Program and Erase Voltage Margin Test Enable Bit 1 = Program and erase margin test 0 = Normal operation This bit is used to evaluate the program/erase voltage margin. EECPD -- Charge Pump Disable Bit 1 = Disable charge pump 0 = Charge pump is turned on during program/erase EECPRD -- Charge Pump Ramp Disable Bit 1 = Disable charge pump controlled ramp up 0 = Charge pump is turned on progressively during program/erase This bit is known to enhance write/erase endurance of EEPROM cells. ECPM -- Charge Pump Monitor Enable Bit 1 = Output the charge pump voltage on the IRQ/VPP pin 0 = Normal operation MC68HC812A4 -- Rev. 3.0 116 EEPROM Advance Information MOTOROLA EEPROM EEPROM Control Registers 7.4.4 EEPROM Programming Register Address: $00F3 Bit 7 Read: BULKP Write: Reset: 1 0 0 0 0 0 0 0 0 0 BYTE ROW ERASE EELAT EEPGM 6 5 4 3 2 1 Bit 0 Figure 7-5. EEPROM Programming Register (EEPROG) Read: Anytime Write: Varies from bit to bit BULKP -- Bulk Erase Protection Bit 1 = EEPROM protected from bulk or row erase 0 = EEPROM can be bulk erased. Write anytime, if EEPGM = 0 and PROTLCK = 0 BYTE -- Byte and Aligned Word Erase Bit 1 = One byte or one aligned word erase only 0 = Bulk or row erase enabled Write anytime, if EEPGM = 0 ROW -- Row or Bulk Erase Bit (when BYTE = 0) 1 = Erase only one 32-byte row 0 = Erase entire EEPROM array Write anytime, if EEPGM = 0 BYTE and ROW have no effect when ERASE = 0. Table 7-2. Erase Selection Byte 0 0 1 1 Row 0 1 0 1 Block Size Bulk erase entire EEPROM array Row erase 32 bytes Byte or aligned word erase Byte or aligned word erase Advance Information MOTOROLA EEPROM MC68HC812A4 -- Rev. 3.0 117 EEPROM If BYTE = 1 and test mode is not enabled, only the location specified by the address written to the programming latches is erased. The operation is a byte or an aligned word erase depending on the size of written data. ERASE -- Erase Control Bit 1 = EEPROM configuration for erasure 0 = EEPROM configuration for programming Write anytime, if EEPGM = 0 This bit configures the EEPROM for erasure or programming. EELAT -- EEPROM Latch Control Bit 1 = EEPROM address and data bus latches set up for programming or erasing 0 = EEPROM set up for normal reads Write anytime, if EEPGM = 0 NOTE: When EELAT is set, the entire EEPROM is unavailable for reads; therefore, no program residing in the EEPROM can be executed while attempting to program unused EEPROM space. Care should be taken that no references to the EEPROM are used while programming. Interrupts should be turned off if the vectors are in the EEPROM. Timing and any serial communications must be done with polling during the programming process. BYTE, ROW, ERASE, and EELAT bits can be written simultaneously or in any sequence. EEPGM -- Program and Erase Enable Bit 1 = Applies program/erase voltage to EEPROM 0 = Disables program/erase voltage to EEPROM The EEPGM bit can be set only after EELAT has been set. When EELAT and EEPGM are set simultaneously, EEPGM remains clear but EELAT is set. The BULKP, BYTE, ROW, ERASE, and EELAT bits cannot be changed when EEPGM is set. To complete a program or erase, two successive writes to clear EEPGM and EELAT bits are required before reading the programmed data. A write to an EEPROM location has no effect when EEPGM is set. Latched address and data cannot be modified during program or erase. MC68HC812A4 -- Rev. 3.0 118 EEPROM Advance Information MOTOROLA EEPROM EEPROM Control Registers A program or erase operation should follow this sequence: 1. Write BYTE, ROW, and ERASE to the desired value; write EELAT = 1. 2. Write a byte or an aligned word to an EEPROM address. 3. Write EEPGM = 1. 4. Wait for programming (tPROG) or erase (tErase) delay time. 5. Write EEPGM = 0. 6. Write EELAT = 0. By jumping from step 5 to step 2, it is possible to program/erase more bytes or words without intermediate EEPROM reads. Advance Information MOTOROLA EEPROM MC68HC812A4 -- Rev. 3.0 119 EEPROM MC68HC812A4 -- Rev. 3.0 120 EEPROM Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 8. Memory Expansion and Chip-Select 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 8.3 Generation of Chip-Selects. . . . . . . . . . . . . . . . . . . . . . . . . . .124 8.3.1 Chip-Selects Independent of Memory Expansion . . . . . . .124 8.3.2 Chip-Selects Used in Conjunction with Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . .126 8.4 Chip-Select Stretch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 8.5 Memory Expansion Registers. . . . . . . . . . . . . . . . . . . . . . . . .130 8.5.1 Port F Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 8.5.2 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 8.5.3 Port F Data Direction Register . . . . . . . . . . . . . . . . . . . . . .131 8.5.4 Port G Data Direction Register . . . . . . . . . . . . . . . . . . . . . .131 8.5.5 Data Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 8.5.6 Program Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . .132 8.5.7 Extra Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.5.8 Window Definition Register . . . . . . . . . . . . . . . . . . . . . . . .133 8.5.9 Memory Expansion Assignment Register . . . . . . . . . . . . .134 8.6 Chip-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 8.7 Chip-Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 8.7.1 Chip-Select Control Register 0 . . . . . . . . . . . . . . . . . . . . . .136 8.7.2 Chip-Select Control Register 1 . . . . . . . . . . . . . . . . . . . . . .138 8.7.3 Chip-Select Stretch Registers . . . . . . . . . . . . . . . . . . . . . .139 8.8 Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 121 Memory Expansion and Chip-Select 8.2 Introduction To use memory expansion, the MCU must be operated in one of the expanded modes. Sections of the standard 64-Kbyte address space have memory expansion windows which allow an external address space larger than 64 Kbytes. Memory expansion consists of three memory expansion windows and six address lines which are used in addition to the standard 16 address lines. The memory expansion function reuses as many as six of the standard 16 address lines. To do this, some of the upper address lines of internal addresses falling in an active window are overridden. Consequently, the address viewed externally may not match the internal address. Usage of chip-selects identify the source of the internal address for debugging and selection of the proper external devices. All memory expansion windows have a fixed size and two have a fixed address location. The third has two selectable address locations. When an internal address falls into one of these active windows, it is translated as shown in Table 8-1. Addresses ADDR9-ADDR0 are not affected by memory expansion and are the same externally as they are internally. Addresses ADDR21-ADDR16 are generated only by memory expansion and are individually enabled by software-programmable control bits. If not enabled, they may be used as general-purpose I/O (input/output). Addresses ADDR15-ADDR10 can be the internal addresses or they can be modified by the memory expansion module. These are not available as general-purpose I/O in expanded modes. MC68HC812A4 -- Rev. 3.0 122 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Introduction Table 8-1. Memory Expansion Values(1) Internal Address $0000-$03FF EWDIR(2)= 1, EWEN = 1 $0000-$03FF EWDIR or EWEN = 0 $0400-$07FF EWDIR = 0, EWEN = 1 $0400-$07FF EWDIR = 1, EWEN = x or EWDIR = x, EWEN = 0 $0800-$6FFF $7000-$7FFF DWEN = 1 $7000-$7FFF DWEN = 0 $8000-$BFFF PWEN = 1 $8000-$BFFF PWEN = 0 $C000-$FFFF A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 1 1 1 1 PEA17 PEA16 PEA15 PEA14 PEA13 PEA12 PEA11 PEA10 1 1 1 1 1 1 A15 A14 A13 A12 A11 A10 1 1 1 1 PEA17 PEA16 PEA15 PEA14 PEA13 PEA12 PEA11 PEA10 1 1 1 1 1 1 A15 A14 A13 A12 A11 A10 1 1 1 1 1 1 1 1 1 1 A15 A14 A13 A12 A11 A11 A11 A11 A11 A11 A10 A10 A10 A10 A10 A10 PDA19 PDA18 PDA17 PDA16 PDA15 PDA14 PDA13 PDA12 1 1 PPA18 1 1 1 PPA17 1 1 1 PPA16 1 1 A15 PPA15 A15 A15 A14 PPA14 A14 A14 A13 A13 A13 A13 A12 A12 A12 A12 PPA21 PPA20 PPA19 1 1 1 1 1 1 1. All port G assigned to memory expansion 2. The EWDIR bit in the MISC register selects the E window address (1 = $0000-$03FF including direct space and 0 = $0400-$07FF). Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 123 Memory Expansion and Chip-Select 8.3 Generation of Chip-Selects To use chip-selects the MCU must be in one of the expanded modes. Each of the seven chip-selects has an address space for which it is active -- that is, when the current CPU address is in the range of that chip-select, it becomes active. Chip-selects are generally used to reduce or eliminate external address decode logic. These active low signals usually are connected directly to the chip-select pin of an external device. 8.3.1 Chip-Selects Independent of Memory Expansion Three types of chip-selects are program memory chip-selects, other memory chip-selects and peripheral chip-selects. Memory chip-selects cover a medium-to-large address space. Peripheral chip-selects (CS3-CS0) cover a small address space. The program memory chip-select includes the vector space and is generally used with non-volatile memory. To start the user's program, the program chip-select is designed to be active out of reset. This is the only chip-select which has a functional difference from the others, so a small memory could use a peripheral chip-select and a peripheral could use a memory chip-select. Figure 8-1 shows peripheral chip-selects in an expanded portion of the memory map. Table 8-2 shows the register settings that correspond to the example. Chip-selects CS2-CS0 always map to the same 2-Kbyte block as the internal register space. The internal registers cover the first 512 bytes and these chip-selects cover all or part of the 512 bytes following the register space blocking out a full 1-Kbyte space. CS3 can map with these other chip-selects or be used in a 1-Kbyte space by itself which starts at either $0000 or $0400. CS3 can be used only for a 1-Kbyte space when it selects the E page of memory expansion and E page is active. MC68HC812A4 -- Rev. 3.0 124 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Generation of Chip-Selects INTERNAL SPACE $0000 $0100 $0200 $0300 $0400 $0500 $0600 $0700 $0800 $0900 $0A00 $0B00 REGISTERS RAM 1 KBYTE EXTERNAL SPACE CS3 1 KBYTE CS0 256 BYTES CS1 $0C00 CS2 $0D00 $0E00 $0F00 $0FFF 128 BYTES 128 BYTES Figure 8-1. Chip-Selects CS3-CS0 Partial Memory Map Table 8-2. Example Register Settings Register INITRM INITRG WINDEF MXAR Value $00 $08 $20 $00 Meaning Assigns internal RAM to $0000-$0FFF Assigns register block to $0800-$09FF and register-following chip-selects at $0A00-$0BFF Enable EPAGE No port G lines assigned as extended address Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 125 Memory Expansion and Chip-Select Table 8-2. Example Register Settings (Continued) Register CSCTL0 CSCTL1 MISC EPAGE Value $xF $x8 Meaning Enables CS3, CS2, CS1, and CS0 Makes CS3 follow EPAGE %0xxxxxxx Puts EPAGE at $0400-$07FF $01 Keeps the translated value of the upper addresses the same as it would have been before translation; not necessary if all external devices use chip-selects CS3 can be used with a 1-Kbyte space in systems not using memory expansion. However, it must be made to appear as if memory expansion is in use. One of many possible configurations is: * * * * * Select the desired 1-Kbyte space for EPAGE (EWDIR in MISC in the MMI). Write the EPAGE register with $0000, if EWDIR is one or $0001 if EWDIR is 0. Designate all port G pins as I/O. Enable EPAGE and CS3. Make CS3 follow EPAGE. 8.3.2 Chip-Selects Used in Conjunction with Memory Expansion Memory expansion and chip-select functions can work independently, but systems requiring memory expansion perform better when chip-selects are also used. For each memory expansion window there is a chip-select (or two) designed to function with it. Figure 8-2 shows a memory expansion and chip-select example using three chip-selects. Table 8-3 shows the register settings that correspond to the example. The program space consists of 128 Kbytes of addressable memory in eight 16-Kbyte pages. Page 7 is always accessible in the space from $C000 to $FFFF. The data space consists of 64 Kbytes of addressable memory in 16, 4-Kbyte pages. Unless CSD is used to select the external RAM, pages 0 through 6 appear in the $0000 to $6FFF space wherever there is no higher priority resource. The MC68HC812A4 -- Rev. 3.0 126 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Generation of Chip-Selects extra space consists of four, 1-Kbyte pages making 4 Kbytes of addressable memory. If memory is increased to the maximum in this example, the program space will consist of 4 Mbytes of addressable space with 256 16-Kbyte pages and page $FF always available. The data space will be 1 Mbyte of addressable space with 256 4-Kbyte pages and pages $F0 to $F6 mirrored to the $0000 to $6FFF space. The extra space will be 256 Kbytes of addressable space in 256 1-Kbyte pages. INTERNAL SPACE $0000 REGISTERS & RAM & CS[3:0] $1000 EEPROM $2000 $3000 $4000 EXTERNAL SPACE 0 1 CHIP-SELECT 3: (CS3) $0400 TO $07FF 2 PAGE 3 DATA CHIP-SELECT: (CSD) $0000 TO $7FFF DATA WINDOW: $7000 to $7FFF ... NOTE 1 xC xD xB xE PAGE xF x4 $5000 x5 $6000 x6 $7000 x0 $8000 $9000 $A000 $B000 $C000 $D000 $E000 $F000 $FFFF VECTORS $FFC0-$FFFF 0 x1 x2 x4 x3 x5 x6 x7 x8 x9 xA NOTE 1: Some 4-Kbyte blocks of physical external data memory can be selected by an access to $0000-$6FFF in the 64-Kbyte map or as pages 0 through 6 in the data window. On-chip registers, EEPROM, and EPAGE have higher priority than CSD. NOTE 2: The last page of physical program memory can be selected by an access to $C000-$FFFF in the 64-Kbyte map or as page 7 in the program window. PAGE 7 1 2 3 4 5 6 NOTE 2 PROGRAM CHIP-SELECT 0: (CSP0) $8000 TO $FFFF PROGRAM PAGES: $8000 to $BFFF Figure 8-2. Memory Expansion and Chip-Select Example Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 127 Memory Expansion and Chip-Select Table 8-3. Example Register Settings Register WINDEF MXAR CSCTL0 CSCTL1 MISC Value $E0 $01 %00111xxx $18 %0xxxxxxx Meaning Enable EPAGE, DPAGE, PPAGE Port G bit 0 assigned as extended address ADDR16 Enables CSP0, CSD, and CS3 Makes CSD follow $0000-$7FFF and CS3 select EPAGE Puts EPAGE at $0400-$09FF 8.4 Chip-Select Stretch Each chip-select can be chosen to stretch bus cycles associated with it. Stretch can be zero, one, two or three whole cycles added which allows interfacing to external devices which cannot meet full bus speed timing. Figure 8-3, Figure 8-4, Figure 8-5, and Figure 8-6 show the waveforms for zero to three cycles of stretch. INTERNAL E-CLOCK CS ECLK PIN UNSTRETCHED BUS CYCLE Figure 8-3. Chip-Select with No Stretch INTERNAL E-CLOCK CS STRETCHED ECLK PIN STRETCHED BY 1 CYCLE Figure 8-4. Chip-Select with One-Cycle Stretch MC68HC812A4 -- Rev. 3.0 128 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Chip-Select Stretch INTERNAL E-CLOCK CS STRETCHED ECLK PIN STRETCHED BY 2 CYCLES Figure 8-5. Chip-Select with 2-Cycle Stretch INTERNAL E-CLOCK CS STRETCHED ECLK PIN STRETCHED BY 3 CYCLES Figure 8-6. Chip-Select with 3-Cycle Stretch The external E-clock may be the stretched E-clock, the E-clock, or no clock depending on the selection of control bits ESTR and IVIS in the MODE register and NECLK in the PEAR register. Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 129 Memory Expansion and Chip-Select 8.5 Memory Expansion Registers This section describes the memory expansion registers. 8.5.1 Port F Data Register Address: $0030 Bit 7 Read: Write: Reset: Alternate pin function: 0 0 6 PF6 0 CSP1 5 PF5 0 CSP0 4 PF4 0 CSD 3 PF3 0 CS3 2 PF2 0 CS2 1 PF1 0 CS1 Bit 0 PF0 0 CS0 = Unimplemented Figure 8-7. Port F Data Register (PORTF) Read: Anytime Write: Anytime Seven port F pins are associated with chip-selects. Any pin not used as a chip-select can be used as general-purpose I/O. All pins are pulled up when inputs (if pullups are enabled). Enabling a chip-select overrides the associated data direction bit and port data bit. 8.5.2 Port G Data Register Address: $0031 Bit 7 Read: Write: Reset: Alternate pin function: 0 0 0 6 0 5 Bit 5 0 ADDR21 4 Bit 4 0 ADDR20 3 Bit 3 0 ADDR19 2 Bit 2 0 ADDR18 1 Bit 1 0 ADDR17 Bit 0 Bit 0 0 ADDR16 = Unimplemented Figure 8-8. Port G Data Register (PORTG) Read: Anytime Write: Anytime Six port G pins are associated with memory expansion. Any pin not used for memory expansion can be used as general-purpose I/O. All pins are pulled up when inputs (if pullups are enabled). Enabling a memory expansion address with the memory expansion assignment register overrides the associated data direction bit and port data bit. MC68HC812A4 -- Rev. 3.0 130 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Memory Expansion Registers 8.5.3 Port F Data Direction Register Address: $0032 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 8-9. Port F Data Direction Register (DDRF) Read: Anytime Write: Anytime When port F is active, DDRF determines pin direction. 1 = Associated bit is an output. 0 = Associated bit is an input. 8.5.4 Port G Data Direction Register Address: $0033 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0 5 4 3 2 1 Bit 0 = Unimplemented Figure 8-10. Port G Data Direction Register (DDRG) Read: Anytime Write: Anytime When port G is active, DDRG determines pin direction. 1 = Associated bit is an output. 0 = Associated bit is an input. Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 131 Memory Expansion and Chip-Select 8.5.5 Data Page Register Address: $0034 Bit 7 Read: Write: Reset: PD19 0 6 PD18 0 5 PD17 0 4 PD16 0 3 PD15 0 2 PD14 0 1 PD13 0 Bit 0 PD12 0 Figure 8-11. Data Page Register (DPAGE) Read: Anytime Write: Anytime When enabled (DWEN = 1), the value in this register determines which of the 256 4-Kbyte pages is active in the data window. An access to the data page memory area ($7000 to $7FFF) forces the contents of DPAGE to address pins ADDR15-ADDR12 and expansion address pins ADDR19-ADDR16. Bits ADDR20 and ADDR21 are forced to 1 if enabled by MXAR. Data chip-select (CSD) must be used in conjunction with this memory expansion window. 8.5.6 Program Page Register Address: $0035 Bit 7 Read: Write: Reset: PPA21 0 6 PPA20 0 5 PPA19 0 4 PPA18 0 3 PPA17 0 2 PPA16 0 1 PPA15 0 Bit 0 PPA14 0 Figure 8-12. Program Page Register (PPAGE) Read: Anytime Write: Anytime When enabled (PWEN = 1), the value in this register determines which of the 256 16-Kbyte pages is active in the program window. An access to the program page memory area ($8000 to $BFFF) forces the contents of PPAGE to address pins ADDR15-ADDR14 and expansion address pins ADDR21-ADDR16. At least one of the program chip-selects (CSP0 or CSP1) must be used in conjunction with this memory expansion window. This register is used by the CALL and RTC instructions to facilitate automatic program flow changing between pages of program memory. MC68HC812A4 -- Rev. 3.0 132 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Memory Expansion Registers 8.5.7 Extra Page Register Address: $0036 Bit 7 Read: PEA17 Write: Reset: 0 0 0 0 0 0 0 0 PEA16 PEA15 PEA14 PEA13 PEA12 PEA11 PEA10 6 5 4 3 2 1 Bit 0 Figure 8-13. Extra Page Register (EPAGE) Read: Anytime Write: Anytime When enabled (EWEN = 1), the value in this register determines which of the 256 1-Kbyte pages is active in the extra window. An access to the extra page memory area forces the contents of EPAGE to address pins ADDR15-ADDR10 and expansion address pins ADDR16-ADDR17. Address bits ADDR21-ADDR18 are forced to one (if enabled by MXAR). Chip-select 3 set to follow the extra page window (CS3 with CS3EP = 1) must be used in conjunction with this memory expansion window. 8.5.8 Window Definition Register Address: $0037 Bit 7 Read: DWEN Write: Reset: 0 0 0 0 0 0 0 0 PWEN EWEN 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 8-14. Window Definition Register (WINDEF) Read: Anytime Write: Anytime DWEN -- Data Window Enable Bit 1 = Enables paging of the data space (4 Kbytes: $7000-$7FFF) via the DPAGE register 0 = Disables DPAGE Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 133 Memory Expansion and Chip-Select PWEN -- Program Window Enable Bit 1 = Enables paging of the program space (16 Kbytes: $8000-$BFFF) via the PPAGE register 0 = Disables PPAGE EWEN -- Extra Window Enable Bit 1 = Enables paging of the extra space (1 Kbyte) via the EPAGE register 0 = Disables EPAGE 8.5.9 Memory Expansion Assignment Register Address: $0038 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 A21E A20E A19E A18E A17E A16E 5 4 3 2 1 Bit 0 = Unimplemented Figure 8-15. Memory Expansion Assignment Register (MXAR) Read: Anytime Write: Anytime A21E, A20E, A19E, A18E, A17E, and A16E -- Selects the memory expansion pins ADDR21-ADDR16. 1 = Selects memory expansion for the associated bit function, overrides DDRG 0 = Selects general-purpose I/O for the associated bit function In single-chip modes these bits have no effect. MC68HC812A4 -- Rev. 3.0 134 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Chip-Selects 8.6 Chip-Selects The chip-selects are all active low. All pins in the associated port are pulled up when they are inputs and the PUPF bit in PUCR is set. If memory expansion is used, usually chip-selects should be used as well, since some translated addresses can be confused with untranslated addresses that are not in an expansion window. In single-chip modes, enabling the chip-select function does not affect the associated pins. The block of register-following chip-selects CS3-CS0 allows many combinations including: * * * * 512-byte CS0 256-byte CS0 and 256-byte CS1 256-byte CS0, 128-byte CS1, and 128-byte CS2 128-byte CS0, 128-byte CS1, 128-byte CS2, and 128-byte CS3 These register-following chip-selects are available in the 512-byte space next to and higher in address than the 512-byte space which includes the registers. For example, if the registers are located at $0800 to $09FF, then these register-following chip-selects are available in the space from $0A00 to $0BFF. Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 135 Memory Expansion and Chip-Select 8.7 Chip-Select Registers This section describes the chip-select registers. 8.7.1 Chip-Select Control Register 0 Address: $003C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 CSP1E CSP0E CSDE CS3E CS2E CS1E CS0E 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 8-16. Chip-Select Control Register 0 (CSCTL0) Read: Anytime Write: Anytime Bits have no effect on the associated pin in single-chip modes. CSP1E -- Chip-Select Program 1 Enable Bit This bit effectively selects the holes in the memory map. It can be used in conjunction with CSP0 to select between two 2-Mbyte devices based on address ADDR21. 1 = Enables this chip-select which covers the space $8000 to $FFFF or full map $0000 to $FFFF 0 = Disables this chip-select CSP0E -- Chip-Select Program 0 Enable Bit 1 = Enables this chip-select which covers the program space $8000 to $FFFF 0 = Disables this chip-select CSDE -- Chip-Select Data Enable Bit 1 = Enables this chip-select which covers either $0000 to $7FFF (CSDHF = 1) or $7000 to $7FFF (CSDHF = 0) 0 = Disables this chip-select MC68HC812A4 -- Rev. 3.0 136 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Chip-Select Registers CS3E -- Chip-Select 3 Enable Bit 1 = Enables this chip-select which covers a 128-byte space following the register space ($x280-$x2FF or $xA80-$xAFF) Alternately, it can be active for accesses within the extra page window. 0 = Disables this chip-select CS2E -- Chip-Select 2 Enable Bit 1 = Enables this chip-select which covers a 128-byte space following the register space ($x380-$x3FF or $xB80-$xBFF) 0 = Disables this chip-select CS1E -- Chip-Select 1 Enable Bit CS2 and CS3 have a higher precedence and can override CS1 for a portion of this space. 1 = Enables this chip-select which covers a 256-byte space following the register space ($x300-$x3FF or $xB00-$xBFF) 0 = Disables this chip-select CS0E -- Chip-Select 0 Enable Bit CS1, CS2, and CS3 have higher precedence and can override CS0 for portions of this space. 1 = Enables this chip-select which covers a 512-byte space following the register space ($x200-$x3FF or $xA00-$xBFF) 0 = Disables this chip-select Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 137 Memory Expansion and Chip-Select 8.7.2 Chip-Select Control Register 1 Address: $003D Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 CSP1FL CSPA21 CSDHF CS3EP 6 5 4 3 2 0 1 0 Bit 0 0 = Unimplemented Figure 8-17. Chip-Select Control Register 1 (CSCTL1) Read: Anytime Write: Anytime CSP1FL -- Program Chip-Select 1 Covers Full Map 1 = If CSPA21 is cleared, chip-select program 1 covers the entire memory map. If CSPA21 is set, this bit has no meaning or effect. 0 = If CSPA21 is cleared, chip-select program 1 covers half the map, $8000 to $FFFF. If CSPA21 is set, this bit has no meaning or effect. CSPA21 -- Program Chip-Select Split Based on ADDR21 Setting this bit allows two 2-Mbyte memories to make up the 4-Mbyte addressable program space. Since ADDR21 is always one in the unpaged $C000 to $FFFF space, CSP0 is active in this space. 1 = Program chip-selects are both active (if enabled) for space $8000 to $FFFF; CSP0 if ADDR21 is set and CSP1 if ADDR21 is cleared. 0 = CSP0 and CSP1 do not rely on ADDR21. CSDHF -- Data Chip-Select Covers Half the Map 1 = Data chip-select covers half the memory map ($0000 to $7FFF) including the optional data page window ($7000 to $7FFF). 0 = Data chip-select covers only $7000 to $7FFF (the optional data page window). MC68HC812A4 -- Rev. 3.0 138 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Chip-Select Registers CS3EP -- Chip-Select 3 Follows Extra Page 1 = Chip-select 3 follows accesses to the 1-Kbyte extra page ($0400 to $07FF or $0000 to $03FF). Any accesses to this window cause the chip-select to go active. (EWEN must be set to 1.) 0 = Chip-select 3 includes only accesses to a 128-byte space following the register space. 8.7.3 Chip-Select Stretch Registers Each of the seven chip-selects has a 2-bit field in this register which determines the amount of clock stretch for accesses in that chip-select space. Read: Anytime Write: Anytime Address: $003E Bit 7 Read: Write: Reset: 0 0 1 1 1 1 1 1 0 6 0 SRP1A SRP1B SRP0A SRP0B STRDA STRDB 5 4 3 2 1 Bit 0 = Unimplemented Figure 8-18. Chip-Select Stretch Register 0 (CSSTR0) Address: $003F Bit 7 Read: STR3A Write: Reset: 0 0 1 1 1 1 1 1 STR3B STR2A STR2B STR1A STR1B STR0A STR0B 6 5 4 3 2 1 Bit 0 Figure 8-19. Chip-Select Stretch Register 1 (CSSTR1) Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 139 Memory Expansion and Chip-Select Table 8-4. Stretch Bit Definition Stretch Bit SxxxA 0 0 1 1 Stretch Bit SxxxB 0 1 0 1 Number of E-Clocks Stretched 0 1 2 3 8.8 Priority Only one module or chip-select may be selected at a time. If more than one module shares a space, only the highest priority module is selected. Table 8-5. Module Priorities Priority Highest Module or Space On-chip register space -- 512 bytes fully blocked for registers although some of this space is unused BDM space (internal) -- When BDM is active, this 256-byte block of registers and ROM appear at $FFxx; cannot overlap RAM or registers On-chip RAM On-chip EEPROM (if enabled, EEON = 1) E space (external) (1) -- 1 Kbyte at either $0000 to $03FF or $0400 to $07FF; may be used with "extra" memory expansion and CS3 CS space (external) (1) -- 512 bytes following the 512-byte register space; may be used with CS3-CS0 P space (external) (1) -- 16 Kbytes fixed at $8000 to $BFFF; may be used with program memory expansion and CSP0 and/or CSP1 D space (external) (1) -- 4 Kbytes fixed at $7000 to $7FFF; may be used with data memory expansion and CSD or CSP1 (if set for full memory space) or the entire half of memory space $0000-$7FFF Lowest Remaining external (1) 1. External spaces can be accessed only if the MCU is in expanded mode. Priorities of different external spaces affect chip-selects and memory expansion. MC68HC812A4 -- Rev. 3.0 140 Memory Expansion and Chip-Select Advance Information MOTOROLA Memory Expansion and Chip-Select Priority Only one chip-select is active at any address. In the event that two or more chip-selects cover the same address, only the highest priority chip-select is active. Chip-selects have this order of priority: Highest CS3 CS2 CS1 CS0 CSP0 CSD Lowest CSP1 Advance Information MOTOROLA Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 141 Memory Expansion and Chip-Select MC68HC812A4 -- Rev. 3.0 142 Memory Expansion and Chip-Select Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 9. Key Wakeups 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.3 Key Wakeup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.3.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 9.3.2 Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . .145 9.3.3 Port D Key Wakeup Interrupt Enable Register . . . . . . . . . .145 9.3.4 Port D Key Wakeup Flag Register . . . . . . . . . . . . . . . . . . .146 9.3.5 Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.3.6 Port H Data Direction Register . . . . . . . . . . . . . . . . . . . . . .147 9.3.7 Port H Key Wakeup Interrupt Enable Register . . . . . . . . . .147 9.3.8 Port H Key Wakeup Flag Register . . . . . . . . . . . . . . . . . . .148 9.3.9 Port J Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.3.10 Port J Data Direction Register . . . . . . . . . . . . . . . . . . . . . .149 9.3.11 Port J Key Wakeup Interrupt Enable Register . . . . . . . . . .149 9.3.12 Port J Key Wakeup Flag Register . . . . . . . . . . . . . . . . . . .150 9.3.13 Port J Key Wakeup Polarity Register . . . . . . . . . . . . . . . . .150 9.3.14 Port J Pullup/Pulldown Select Register . . . . . . . . . . . . . . .151 9.3.15 Port J Pullup/Pulldown Enable Register. . . . . . . . . . . . . . .152 9.2 Introduction The key wakeup feature of the MC68HC812A4 issues an interrupt that wakes up the CPU when it is in stop or wait mode. Three ports are associated with the key wakeup function: port D, port H, and port J. Port D and port H wakeups are triggered with a falling signal edge. Port J key wakeups have a selectable falling or rising signal edge as the active edge. For each pin which has an interrupt enabled, there is a path to the interrupt request signal which has no clocked devices when the part is in stop mode. This allows an active edge to bring the part out of stop. Advance Information MOTOROLA Key Wakeups MC68HC812A4 -- Rev. 3.0 143 Key Wakeups Default register addresses, as established after reset, are indicated in the following descriptions. For information on remapping the register block, refer to Section 5. Operating Modes and Resource Mapping. 9.3 Key Wakeup Registers This section provides a summary of the key wakeup registers. 9.3.1 Port D Data Register Address: $0005 Bit 7 Read: PD7 Write: Reset: Alternate pin function: 0 KWD7 0 KWD6 0 KWD5 0 KWD4 0 KWD3 0 KWD2 0 KWD1 0 KWD0 PD6 PD5 PD4 PD3 PD2 PD1 PD0 6 5 4 3 2 1 Bit 0 Figure 9-1. Port D Data Register (PORTD) This register is not in the map in wide expanded modes or in special expanded narrow mode with MODE register bit EMD set. An interrupt is generated when a bit in the KWIFD register and its corresponding KWIED bit are both set. These bits correspond to the pins of port D. All eight bits/pins share the same interrupt vector and can wake the CPU when it is in stop or wait mode. Key wakeups can be used with the pins configured as inputs or outputs. Key wakeup port D shares a vector and control bit with IRQ. IRQEN must be set for key wakeup interrupts to signal the CPU. MC68HC812A4 -- Rev. 3.0 144 Key Wakeups Advance Information MOTOROLA Key Wakeups Key Wakeup Registers 9.3.2 Port D Data Direction Register Address: $0007 Bit 7 Read: Write: Reset: Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 Bit 0 Bit 0 0 Figure 9-2. Port D Data Direction Register (DDRD) Read: Anytime Write: Anytime This register is not in the map in wide expanded modes or in special expanded narrow mode with MODE register bit EMD set. Data direction register D is associated with port D and designates each pin as an input or output. DDRD7-DDRD0 -- Data Direction Port D Bits 1 = Associated pin is an output. 0 = Associated pin is an input. 9.3.3 Port D Key Wakeup Interrupt Enable Register Address: $0020 Bit 7 Read: Write: Reset: Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 Bit 0 Bit 0 0 Figure 9-3. Port D Key Wakeup Interrupt Enable Register (KWIED) Read: Anytime Write: Anytime This register is not in the map in wide expanded modes and in special expanded narrow mode with MODE register bit EMD set. KWIED7-KWIED0 -- Key Wakeup Port D Interrupt Enable Bits 1 = Interrupt for the associated bit is enabled. 0 = Interrupt for the associated bit is disabled. Advance Information MOTOROLA Key Wakeups MC68HC812A4 -- Rev. 3.0 145 Key Wakeups 9.3.4 Port D Key Wakeup Flag Register Address: $0021 Bit 7 Read: Write: Reset: Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 Bit 0 Bit 0 0 Figure 9-4. Port D Key Wakeup Flag Register (KWIFD) Read: Anytime Write: Anytime Each flag is set by a falling edge on its associated input pin. To clear the flag, write 1 to the corresponding bit in KWIFD. This register is not in the map in wide expanded modes or in special expanded narrow mode with MODE register bit EMD set. KWIFD7-KWIFD0 -- Key Wakeup Port D Flags 1 = Falling edge on the associated bit has occurred. An interrupt occurs if the associated enable bit is set. 0 = Falling edge on the associated bit has not occurred. 9.3.5 Port H Data Register Address: $0024 Bit 7 Read: Write: Reset: Alternate pin function: PH7 0 KWH7 6 PH6 0 KWH6 5 PH5 0 KWH5 4 PH4 0 KWH4 3 PH3 0 KWH3 2 PH2 0 KWH2 1 PH1 0 KWH1 Bit 0 PH0 0 KWH0 Figure 9-5. Port H Data Register (PORTH) Read: Anytime Write: Anytime Port H is associated with key wakeup H. Key wakeups can be used with the pins designated as inputs or outputs. DDRH determines whether each pin is an input or output. MC68HC812A4 -- Rev. 3.0 146 Key Wakeups Advance Information MOTOROLA Key Wakeups Key Wakeup Registers 9.3.6 Port H Data Direction Register Address: $0025 Bit 7 Read: DDRH7 Write: Reset: 0 0 0 0 0 0 0 0 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 6 5 4 3 2 1 Bit 0 Figure 9-6. Port H Data Direction Register (DDRH) Read: Anytime Write: Anytime Data direction register H is associated with port H and designates each pin as an input or output. DDRH7-DDRH0 -- Data Direction Port H Bits 1 = Associated pin is an output. 0 = Associated pin is an input. 9.3.7 Port H Key Wakeup Interrupt Enable Register Address: $0026 Bit 7 Read: KWIEH7 Write: Reset: 0 0 0 0 0 0 0 0 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEH0 6 5 4 3 2 1 Bit 0 Figure 9-7. Port H Key Wakeup Interrupt Enable Register (KWIEH) An interrupt is generated when a bit in the KWIFH register and its corresponding KWIEH bit are both set. These bits correspond to the pins of port H. KWIEH7-KWIEH0 -- Key Wakeup Port H Interrupt Enable Bits 1 = Interrupt for the associated bit is enabled. 0 = Interrupt for the associated bit is disabled. Advance Information MOTOROLA Key Wakeups MC68HC812A4 -- Rev. 3.0 147 Key Wakeups 9.3.8 Port H Key Wakeup Flag Register Address: $0027 Bit 7 Read: KWIFH7 Write: Reset: 0 0 0 0 0 0 0 0 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFH0 6 5 4 3 2 1 Bit 0 Figure 9-8. Port H Key Wakeup Flag Register (KWIFH) Read: Anytime Write: Anytime Each flag is set by a falling edge on its associated input pin. To clear the flag, write one to the corresponding bit in KWIFH. KWIFH7-KWIFH0 -- Key Wakeup Port H Flags 1 = Falling edge on the associated bit has occurred (an interrupt occurs if the associated enable bit is set) 0 = Falling edge on the associated bit has not occurred 9.3.9 Port J Data Register Address: $0028 Bit 7 Read: PJ7 Write: Reset: Alternate pin function: 0 KWJ7 0 KWJ6 0 KWJ5 0 KWJ2 0 KWJ4 0 KWJ2 0 KWJ1 0 KWJ0 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 6 5 4 3 2 1 Bit 0 Figure 9-9. Port J Data Register (PORTJ) Read: Anytime Write: Anytime Port J is associated with key wakeup J. Key wakeups can be used with the pins designated as inputs or outputs. DDRJ determines whether each pin is an input or output. MC68HC812A4 -- Rev. 3.0 148 Key Wakeups Advance Information MOTOROLA Key Wakeups Key Wakeup Registers 9.3.10 Port J Data Direction Register Address: $0029 Bit 7 Read: DDRJ7 Write: Reset: 0 0 0 0 0 0 0 0 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 6 5 4 3 2 1 Bit 0 Figure 9-10. Port J Data Direction Register (DDRJ) Determines direction of each port J pin. DDRJ7-DDRJ0 -- Data Direction Port J 1 = Associated pin is an output. 0 = Associated pin is an input. 9.3.11 Port J Key Wakeup Interrupt Enable Register Address: $002A Bit 7 Read: KWIEJ7 Write: Reset: 0 0 0 0 0 0 0 0 KWIEJ6 KWIEJ5 KWIEJ4 KWIEJ3 KWIEJ2 KWIEJ1 KWIEJ0 6 5 4 3 2 1 Bit 0 Figure 9-11. Port J Key Wakeup Interrupt Enable Register (KWIEJ) Read: Anytime Write: Anytime An interrupt is generated when a bit in the KWIFJ register and its corresponding KWIEJ bit are both set. These bits correspond to the pins of port J. All eight bits/pins share the same interrupt vector. KWIEJ7-KWIEF0 -- Key Wakeup Port J Interrupt Enable Bits 1 = Interrupt for the associated bit is enabled. 0 = Interrupt for the associated bit is disabled. Advance Information MOTOROLA Key Wakeups MC68HC812A4 -- Rev. 3.0 149 Key Wakeups 9.3.12 Port J Key Wakeup Flag Register Address: $002B Bit 7 Read: KWIFJ7 Write: Reset: 0 0 0 0 0 0 0 0 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0 6 5 4 3 2 1 Bit 0 Figure 9-12. Port J Key Wakeup Flag Register (KWIFJ) Read: Anytime Write: Anytime Each flag gets set by an active edge on the associated input pin. This could be a rising or falling edge based on the state of the KPOLJ register. To clear the flag, write 1 to the corresponding bit in KWIFJ. Initialize this register after initializing KPOLJ so that illegal flags can be cleared. KWIFJ7-KWIFJ0 -- Key Wakeup Port J Flags 1 = An active edge on the associated bit has occurred. An interrupt occurs if the associated enable bit is set. 0 = An active edge on the associated bit has not occurred. 9.3.13 Port J Key Wakeup Polarity Register Address: $002C Bit 7 Read: KPOLJ7 Write: Reset: 0 0 0 0 0 0 0 0 KPOLJ6 KPOLJ5 KPOLJ4 KPOLJ3 KPOLJ2 KPOLJ1 KPOLJ0 6 5 4 3 2 1 Bit 0 Figure 9-13. Port J Key Wakeup Polarity Register (KPOLJ) Read: Anytime Write: Anytime MC68HC812A4 -- Rev. 3.0 150 Key Wakeups Advance Information MOTOROLA Key Wakeups Key Wakeup Registers It is best to clear the flags after initializing this register because changing the polarity of a bit can cause the associated flag to set. KPOLJ7-KPOLJ0 -- Key Wakeup Port J Polarity Select Bits 1 = Rising edge on the associated port J pin sets the associated flag bit in the KWIFJ register. 0 = Falling edge on the associated port J pin sets the associated flag bit in the KWIFJ register. 9.3.14 Port J Pullup/Pulldown Select Register Address: $002D Bit 7 Read: PUPSJ7 Write: Reset: 0 0 0 0 0 0 0 0 PUPSJ6 PUPSJ5 PUPSJ4 PUPSJ3 PUPSJ2 PUPSJ1 PUPSJ0 6 5 4 3 2 1 Bit 0 Figure 9-14. Port J Pullup/Pulldown Select Register (PUPSJ) Read: Anytime Write: Anytime Each bit in the register corresponds to a port J pin. Each bit selects a pullup or pulldown device for the associated port J pin. The pullup or pulldown is active only if enabled by the PULEJ register. PUPSJ should be initialized before enabling the pullups/pulldowns (PUPEJ). PUPSJ7-PUPSJ0 -- Key Wakeup Port J Pullup/Pulldown Select Bits 1 = Pullup is selected for the associated port J pin. 0 = Pulldown is selected for the associated port J pin. Advance Information MOTOROLA Key Wakeups MC68HC812A4 -- Rev. 3.0 151 Key Wakeups 9.3.15 Port J Pullup/Pulldown Enable Register Address: $002E Bit 7 Read: PULEJ7 Write: Reset: 0 0 0 0 0 0 0 0 PULEJ6 PULEJ5 PULEJ4 PULEJ3 PULEJ2 PULEJ1 PULEJ0 6 5 4 3 2 1 Bit 0 Figure 9-15. Port J Pullup/Pulldown Enable Register (PULEJ) Read: Anytime Write: Anytime Each bit in the register corresponds to a port J pin. If a pin is configured as an input, each bit enables an active pullup or pulldown device. PUPSJ selects whether a pullup or a pulldown is the active device. PULEJ7-PULEJ0 -- Key Wakeup Port J Pullup/Pulldown Enable Bits 1 = Selected pullup/pulldown device for the associated port J pin is enabled if it is an input. 0 = Associated port J pin has no pullup/pulldown device. MC68HC812A4 -- Rev. 3.0 152 Key Wakeups Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 10. Clock Module 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 10.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 10.3.1 Clock Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 10.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 10.5.1 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . .156 10.5.2 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10.5.3 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10.5.4 Peripheral Clock Divider Chains. . . . . . . . . . . . . . . . . . . . .158 10.6 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .161 10.6.1 Real-Time Interrupt Control Register . . . . . . . . . . . . . . . . .161 10.6.2 Real-Time Interrupt Flag Register . . . . . . . . . . . . . . . . . . .163 10.6.3 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.6.4 Arm/Reset COP Timer Register . . . . . . . . . . . . . . . . . . . . .166 Advance Information MOTOROLA Clock Module MC68HC812A4 -- Rev. 3.0 153 Clock Module 10.2 Introduction Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MCU. 10.3 Block Diagram REGISTER: CLKCTL BITS: BCS[C:B:A] 0:0:0 MUXCLK /2 XTAL OSCILLATOR EXTAL /2 0:1:0 0:0:1 SYSCLK /2 E- AND P-CLOCK GENERATOR ECLK PCLK REGISTER: CLKCTL BITS: MCS[B:A] 0:0 MCLK 0:1 TO BDM, BUSES, SPI, ATD T-CLOCK GENERATOR TCLK TO CPU /2 0:1:1 /2 /2 PLLS /2 1:0:0 /2 1:0:1 /2 1:1 TO SCI, TIM, PA, RTI, COP PHASE-LOCK LOOP /2 1:1:0 /2 1:1:1 Figure 10-1. Clock Module Block Diagram MC68HC812A4 -- Rev. 3.0 154 Clock Module Advance Information MOTOROLA Clock Module Block Diagram 10.3.1 Clock Generators The clock module generates four types of internal clock signals derived from the oscillator: 1. T-clocks -- Drives the CPU 2. E-clock -- Drives the bus interfaces, BDM, SPI, and ATD 3. P-clock -- Drives the bus interfaces, BDM, SPI, and ATD 4. M-clock -- Drives on-chip modules such as the timer, SCI, RTI, COP, and restart-from-stop delay time Figure 10-2 shows clock timing relationships. Four bits in the CLKCTL register control the base clock and M-clock divide selection (/1, /2, /4, and /8 are selectable). T1CLK T2CLK T3CLK T4CLK INTERNAL ECLK PCLK MCLK 1 MCLK 2 MCLK 4 MCLK 8 Note: The MCLK depends on the chosen divider settings in the CLKCTL register. Figure 10-2. Internal Clock Relationships Advance Information MOTOROLA Clock Module MC68HC812A4 -- Rev. 3.0 155 Clock Module 10.4 Register Map NOTE: The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Addr. Register Name Read: Write: Reset: Read: Write: Reset: COP Control Register (COPCTL) See page 163. Read: Write: Reset: Special reset: Arm/Reset COP Register (COPRST) See page 166. Read: Write: Reset: Bit 7 RTIE 0 RTIF 0 CME 0 0 0 Bit 7 0 6 RSWAI 0 0 5 RSBCK 0 0 4 0 3 RTBYP 0 0 2 RTR2 0 0 1 RTR1 0 0 Bit 0 RTR0 0 0 Real-Time Interrupt $0014 Control Reg. (RTICTL) See page 161. Real-Time Interrupt Flag Register (RTIFLG) $0015 See page 163. 0 0 0 FCME 0 0 0 Bit 6 0 0 FCM 0 0 0 Bit 5 0 0 FCOP 0 0 0 Bit 4 0 0 DISR 0 1 0 Bit 3 0 0 CR2 0 1 0 Bit 2 0 0 CR1 0 1 0 Bit 1 0 0 CR0 0 1 0 Bit 0 0 $0016 $0017 = Unimplemented Figure 10-3. Clock Function Register Map 10.5 Functional Description This section provides a functional description of the MC68HC812A4. 10.5.1 Computer Operating Properly (COP) The COP or watchdog timer is an added check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping a free-running watchdog timer from timing out. If the watchdog timer times out, it is an indication that the software is no MC68HC812A4 -- Rev. 3.0 156 Clock Module Advance Information MOTOROLA Clock Module Functional Description longer being executed in the intended sequence; thus, a system reset is initiated. Three control bits allow selection of seven COP timeout periods. When COP is enabled, sometime during the selected period the program must write $55 and $AA (in this order) to the COPRST register. If the program fails to do this, the part resets. If any value other than $55 or $AA is written, the part resets. 10.5.2 Real-Time Interrupt There is a real-time (periodic) interrupt (RTI) available to the user. This interrupt occurs at one of seven selected rates. An interrupt flag and an interrupt enable bit are associated with this function. The rate select has three bits. 10.5.3 Clock Monitor The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay. If no MCU clock edges are detected within this RC time delay, the clock monitor can generate a system reset. The clock monitor function is enabled/disabled by the CME control bit in the COPCTL register. This timeout is based on an RC delay so that the clock monitor can operate without any MCU clocks. CME enables clock monitor. 1 = Slow or stopped clocks (including the STOP instruction) cause a clock reset sequence. 0 = Clock monitor is disabled. Slow clocks and STOP instruction may be used. Clock monitor timeouts are shown in Table 10-1. Table 10-1. Clock Monitor Timeouts Supply 5 V 10% 3 V 10% Range 2-20 s 5-100 s Advance Information MOTOROLA Clock Module MC68HC812A4 -- Rev. 3.0 157 Clock Module 10.5.4 Peripheral Clock Divider Chains Figure 10-4, Figure 10-5, and Figure 10-6 summarize the peripheral clock divider chains. / 8192 REGISTER: RTICTL BITS: RTR[2:1:0] 0:0:0 REGISTER: COPCTL BITS: CR[2:1:0] 0:0:0 0:0:1 SCI0 BAUD RATE GENERATOR ( 1 TO 8191) 0:0:1 MCLK SCI0 RECEIVE BAUD RATE (16X) SCI0 TRANSMIT BAUD RATE (1X) /2 0:1:0 /4 0:1:0 /2 0:1:1 /4 0:1:1 / 16 /2 1:0:0 /4 1:0:0 SCI1 BAUD RATE GENERATOR ( 1 TO 8191) SCI1 RECEIVE BAUD RATE (16X) SCI1 TRANSMIT BAUD RATE (1X) /2 1:0:1 /4 1:0:1 /2 1:1:0 /4 1:1:0 / 16 /2 1:1:1 /4 1:1:1 TO RTI TO COP Figure 10-4. Clock Chain for SCI0, SCI1, RTI, and COP MC68HC812A4 -- Rev. 3.0 158 Clock Module Advance Information MOTOROLA Clock Module Functional Description TEN REGISTER: TMSK2 BITS: PR[2:0] 0:0:0 REGISTER: PACTL BITS: PAEN:CLK1:CLK0 0:X:X MCLK /2 0:0:1 1:0:0 /2 0:1:0 1:0:1 /2 0:1:1 /2 PULSE ACCUMULATOR LOW BYTE PULSE ACCUMULATOR HIGH BYTE PACLK 256 PACLK 65,536 (PAOV) 1:1:0 1:0:0 1:1:1 /2 1:0:1 /2 GATE LOGIC PACLK TO TIM COUNTER PORT T7 PAMOD PAEN Figure 10-5. Clock Chain for TIM Advance Information MOTOROLA Clock Module MC68HC812A4 -- Rev. 3.0 159 Clock Module PRS[4:0] PCLK 5-BIT ATD PRESCALER /2 ATD CLOCK REGISTER: SP0BR BITS: SPR2:SPR1:SPR0 0:0:0 SPI BIT RATE /2 0:0:1 /2 0:1:0 ECLK BDM BIT CLOCK Receive: Detect falling edge; count 12 E-clocks; sample input Transmit 1: Detect falling edge; count six E-clocks while output is high impedance; drive out one E cycle pulse high; return output to high impedance Transmit 0: Detect falling edge; drive out low; count nine E-clocks; drive out one E cycle pulse high; return output to high-impedance /2 0:1:1 SYNCHRONIZER BKGD IN /2 1:0:0 BKGD DIRECTION BKGD PIN LOGIC /2 1:0:1 BKGD OUT /2 1:1:0 /2 1:1:1 Figure 10-6. Clock Chain for SPI, ATD and BDM MC68HC812A4 -- Rev. 3.0 160 Clock Module Advance Information MOTOROLA Clock Module Registers and Reset Initialization 10.6 Registers and Reset Initialization This section describes the registers and reset initialization. 10.6.1 Real-Time Interrupt Control Register Address: $0014 Bit 7 Read: RTIE Write: Reset: 0 0 0 0 0 0 0 0 RSWAI RSBCK 6 5 4 0 RTBYP RTR2 RTR1 RTR0 3 2 1 Bit 0 = Unimplemented Figure 10-7. Real-Time Interrupt Control Register (RTICTL) Read: Anytime Write: Varies from bit to bit RTIE -- Real-Time Interrupt Enable Bit Write: Anytime RTIE enables interrupt requests generated by the RTIF flag. 1 = RTIF interrupt requests enabled 0 = RTIF interrupt requests disabled RSWAI -- RTI Stop in Wait Bit Write: Once in normal modes, anytime in special modes RSWAI disables the RTI and the COP during wait mode. 1 = RTI and COP disabled in wait mode 0 = RTI and COP enabled in wait mode RSBCK -- RTI Stop in Background Mode Bit Write: Once in normal modes, anytime in special modes RSBCK disables the RTI and the COP during background debug mode. 1 = RTI and COP disabled during background mode 0 = RTI and COP enabled during background mode Advance Information MOTOROLA Clock Module MC68HC812A4 -- Rev. 3.0 161 Clock Module RTBYP -- RTI Bypass Bit Write: Never in normal modes, anytime in special modes RTBYP allows faster testing by causing the divider chain to be bypassed. The divider chain normally divides M by 213. When RTBYP is set, the divider chain divides M by 4. 1 = Divider chain bypass 0 = No divider chain bypass RTR2, RTR1, RTR0 -- Real-Time Interrupt Rate Select Bits Write: Anytime Rate select for real-time interrupt. The clock used for this module is the module (M) clock. Table 10-2. Real-Time Interrupt Rates Real-Time Timeout Period RTR[2:1:0] 000 001 010 011 100 101 110 111 M-Clock Divisor M = 4.0 MHz OFF 213 214 215 216 217 218 219 OFF 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms 131.72 ms M = 8.0 MHz OFF 1.024 ms 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms MC68HC812A4 -- Rev. 3.0 162 Clock Module Advance Information MOTOROLA Clock Module Registers and Reset Initialization 10.6.2 Real-Time Interrupt Flag Register Address: $0015 Bit 7 Read: RTIF Write: Reset: 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 10-8. Real-Time Interrupt Flag Register (RTIFLG) RTIF -- Real-Time Interrupt Flag RTIF is set when the timeout period elapses. RTIF generates an interrupt request if the RTIE bit is set in the RTI control register. Clear RTIF by writing to the real-time interrupt flag register with RTIF set. 1 = Timeout period elapsed 0 = Timeout period not elapsed 10.6.3 COP Control Register Address: $0016 Bit 7 Read: Write: Normal reset: Special reset: CME 0 0 6 FCME 0 0 5 FCM 0 0 4 FCOP 0 0 3 DISR 0 1 2 CR2 0 1 1 CR1 0 1 Bit 0 CR0 0 1 Figure 10-9. COP Control Register (COPCTL) Read: Anytime Write: Varies from bit to bit Advance Information MOTOROLA Clock Module MC68HC812A4 -- Rev. 3.0 163 Clock Module CME -- Clock Monitor Enable Bit Write: Anytime CME enables the clock monitor. If the force clock monitor enable bit, FCME, is set, CME has no meaning or effect. 1 = Clock monitor enabled 0 = Clock monitor disabled NOTE: Clear the CME bit before executing a STOP instruction and set the CME bit after exiting stop mode. FCME -- Force Clock Monitor Enable Bit Write: Once in normal modes, anytime in special modes FCME forces the clock monitor to be enabled until a reset occurs. When FCME is set, the CME bit has no effect. 1 = Clock monitor enabled 0 = CME bit enables or disables clock monitor NOTE: Clear the FCME bit in applications that use the STOP instruction and the clock monitor. FCM -- Force Clock Monitor Reset Bit Write: Never in normal modes, anytime in special modes FCM forces a reset when the clock monitor is enabled and detects a slow or stopped clock. 1 = Clock monitor reset enabled 0 = Normal operation NOTE: When the disable reset bit, DISR, is set, FCM has no effect. FCOP -- Force COP Reset Bit Write: Never in normal modes; anytime in special modes FCOP forces a reset when the COP is enabled and times out. 1 = COP reset enabled 0 = Normal operation NOTE: When the disable reset bit, DISR, is set, FCOP has no effect. MC68HC812A4 -- Rev. 3.0 164 Clock Module Advance Information MOTOROLA Clock Module Registers and Reset Initialization DISR -- Disable Reset Bit Write: Never in normal modes; anytime in special modes DISR disables clock monitor resets and COP resets. 1 = Clock monitor and COP resets disabled 0 = Normal operation CR2, CR1, and CR0 -- COP Watchdog Timer Rate Select Bits Write: Once in normal modes, anytime in special modes The COP system is driven by a constant frequency of M/213. These bits specify an additional division factor to arrive at the COP timeout rate. (The clock used for this module is the M-clock.) Table 10-3. COP Watchdog Rates COP Timeout Period 0/+2.048 ms 0/+1.024 ms M = 4.0 MHz 000 001 010 011 100 101 110 111 OFF 213 215 217 219 221 222 223 OFF 2.048 ms 8.1920 ms 32.768 ms 131.072 ms 524.288 ms 1.048 s 2.097 s M = 8.0 MHz OFF 1.024 ms 4.096 ms 16.384 ms 65.536 ms 262.144 ms 524.288 ms 1.048576 s CR[2:1:0] M-Clock Divisor Advance Information MOTOROLA Clock Module MC68HC812A4 -- Rev. 3.0 165 Clock Module 10.6.4 Arm/Reset COP Timer Register Address: $0017 Bit 7 Read: Write: Reset: 0 Bit 7 0 6 0 Bit 6 0 5 0 Bit 5 0 4 0 Bit 4 0 3 0 Bit 3 0 2 0 Bit 2 0 1 0 Bit 1 0 Bit 0 0 Bit 0 0 Figure 10-10. Arm/Reset COP Timer Register (COPRST) To restart the COP timeout period and avoid a COP reset, write $55 and then $AA to this address before the end of the COP timeout period. Other instructions can be executed between these writes. Writing anything other than $55 or $AA causes a COP reset to occur. MC68HC812A4 -- Rev. 3.0 166 Clock Module Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 11. Phase-Lock Loop (PLL) 11.1 Contents 11.2 11.3 11.4 11.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.6 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .171 11.6.1 Loop Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.6.2 Reference Divider Registers . . . . . . . . . . . . . . . . . . . . . . .172 11.6.3 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.2 Introduction The phase-lock loop (PLL) allows slight adjustments in the frequency of the MCU. The smallest increment of adjustment is 9.6 kHz to the output frequency (FOut) rate assuming an input clock of 16.8 MHz (OSCXTAL) and a reference divider set to 1750. Figure 11-1 shows the PLL dividers and a portion of the clock module and Figure 11-2 provides a register map. Advance Information MOTOROLA Phase-Lock Loop (PLL) MC68HC812A4 -- Rev. 3.0 167 Phase-Lock Loop (PLL) 11.3 Block Diagram VDDPLL LOOP FILTER SEE Table 11-1 RDV[11:0] REFERENCE DIVIDER fReference UP PHASE DETECTOR fLoop PLLON DOWN RS CS CP XFC PIN CHARGE PUMP XTAL PIN OSCILLATOR EXTAL PIN OUT-OF-LOCK DETECTOR VCO LCKF LOOP DIVIDER DIVIDE BY TWO LDV[11:0] PLLS MUX MUXCLK ECLK TO MPU PCLK ECLK & PCLK GENERATOR SYSCLK BASE CLOCK DIVIDER TO MODULES MCLK MODULE CLOCK DIVIDER TO CPU TCLK TCLK GENERATOR BCS[C:B:A] MCS[B:A] Figure 11-1. PLL Block Diagram MC68HC812A4 -- Rev. 3.0 168 Phase-Lock Loop (PLL) Advance Information MOTOROLA Phase-Lock Loop (PLL) Block Diagram Table 11-1. PLL Filter Values RS 16,778.40524 11,864.12412 3,001.412373 2,450.642941 2,237.120698 2,122.319042 1,898.259859 1,732.866242 1,604.322397 1,500.706187 1,355.8999 1,342.272419 CP = .0033 F E Clock 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 CS 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 0.000000033 Crystal 32,000 64,000 1,000,000 1,500,000 1,800,000 2,000,000 2,500,000 3,000,000 3,500,000 4,000,000 4,900,000 5,000,000 Advance Information MOTOROLA Phase-Lock Loop (PLL) MC68HC812A4 -- Rev. 3.0 169 Phase-Lock Loop (PLL) 11.4 Register Map Addr. Register Name Loop Divider Register High (LDVH) See page 171. Read: Write: Reset: Read: LDV7 Write: Reset: Read: Write: Reset: Read: RDV7 Write: Reset: Read: Write: Reset: 0 0 0 0 0 0 0 0 1 LCKF PLLON PLLS BCSC BCSB BCSA MCSB MCSA 1 1 1 1 1 1 1 RDV6 RDV5 RDV4 RDV3 RDV2 RDV1 RDV0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 RDV11 RDV10 RDV9 RDV8 1 1 1 1 LDV6 LDV5 LDV4 LDV3 LDV2 LDV1 LDV0 0 0 0 0 1 1 1 1 Bit 7 0 6 0 5 0 4 0 LDV11 LDV10 LDV9 LDV8 3 2 1 Bit 0 $0040 $0041 Loop Divider Register Low (LDVL) See page 171. $0042 Reference Divider Register High (RDVH) See page 172. $0043 Reference Divider Register Low (RDVL) See page 172. Clock Control Register $0047 (CLKCTL) See page 173. = Unimplemented Figure 11-2. PLL Register Map 11.5 Functional Description The PLL may be used to run the MCU from a different timebase than the incoming crystal value. If the PLL is selected, it continues to run when it's in wait or stop mode which results in more power consumption than normal. To take full advantage of the reduced power consumption of stop mode, turn off the PLL before going into stop. Although it is possible to set the divider to command a very high clock frequency, do not exceed the 16.8 MHz frequency limit for the MCU. MC68HC812A4 -- Rev. 3.0 170 Phase-Lock Loop (PLL) Advance Information MOTOROLA Phase-Lock Loop (PLL) Registers and Reset Initialization A passive external loop filter must be placed on the control line (XFC pad). The filter is a second-order, low-pass filter to eliminate the VCO input ripple. 11.6 Registers and Reset Initialization This section describes the registers and reset initialization. 11.6.1 Loop Divider Registers Address: $0040 Bit 7 Read: Write: Reset: 0 0 0 0 1 1 1 1 0 6 0 5 0 4 0 LDV11 LDV10 LDV9 LDV8 3 2 1 Bit 0 = Unimplemented Figure 11-3. Loop Divider Register High (LDVH) Address: $0041 Bit 7 Read: LDV7 Write: Reset: 1 1 1 1 1 1 1 1 LDV6 LDV5 LDV4 LDV3 LDV2 LDV1 LDV0 6 5 4 3 2 1 Bit 0 Figure 11-4. Loop Divider Register Low (LDVL) Read: Anytime Write: Anytime If the PLL is on, the count in the loop divider (LDV) 12-bit register effectively multiplies up from the PLL base frequency. CAUTION: Do not exceed the maximum rated operating frequency for the CPU. Advance Information MOTOROLA Phase-Lock Loop (PLL) MC68HC812A4 -- Rev. 3.0 171 Phase-Lock Loop (PLL) 11.6.2 Reference Divider Registers Address: $0042 Bit 7 Read: Write: Reset: 0 0 0 0 1 1 1 1 0 6 0 5 0 4 0 RDV11 RDV10 RDV9 RDV8 3 2 1 Bit 0 = Unimplemented Figure 11-5. Reference Divider Register High (RDVH) Address: $0043 Bit 7 Read: RDV7 Write: Reset: 1 1 1 1 1 1 1 1 RDV6 RDV5 RDV4 RDV3 RDV2 RDV1 RDV0 6 5 4 3 2 1 Bit 0 Figure 11-6. Reference Divider Register Low (RDVL) Read: Anytime Write: Anytime The count in the reference divider (RDV) 12-bit register divides the crystal oscillator clock input. In the reset condition, both LDV and RDV are set to the maximum count which produces an internal frequency at the phase detector of 8.2 kHz and a final output frequency of 16.8 MHz with a 16.8 MHz input clock. MC68HC812A4 -- Rev. 3.0 172 Phase-Lock Loop (PLL) Advance Information MOTOROLA Phase-Lock Loop (PLL) Registers and Reset Initialization 11.6.3 Clock Control Register Address: $0047 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 LCKF PLLON PLLS BCSC BCSB BCSA MCSB MCSA 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 11-7. Clock Control Register (CLKCTL) Read: Anytime Write: Anytime LCKF -- Lock Flag This read-only flag is set when the PLL frequency is at least half the target frequency and no more than twice the target frequency. 1 = PLL locked 0 = PLL not locked PLLON -- PLL On Bit Setting PLLON turns on the PLL. 1 = PLL on 0 = PLL off PLLS -- PLL Select Bit (PLL output or crystal input frequency) PLLS selects the PLL after the LCKF flag is set. 1 = PLL selected 0 = Crystal input selected BCS[C:B:A] -- Base Clock Select Bits These bits determine the frequency of SYSCLK. SYSCLK is the source clock for the MCU, including the CPU and buses. See Table 11-2. SYSCLK and is twice the bus rate. MUXCLK is either the PLL output or the crystal input frequency as selected by the PLLS bit. Advance Information MOTOROLA Phase-Lock Loop (PLL) MC68HC812A4 -- Rev. 3.0 173 Phase-Lock Loop (PLL) Table 11-2. Base Clock Selection BCSC:BCSB:BCSA 000 001 010 011 100 101 110 111 SYSCLK MUXCLK MUXCLK -----------------------2 MUXCLK -----------------------4 8 MUXCLK -----------------------MUXCLK -----------------------16 32 64 MUXCLK -----------------------MUXCLK -----------------------MUXCLK -----------------------128 MCSA and MCSB -- Module Clock Select Bits These bits determine the clock used by some sections of some of the modules such as the baud rate generators of the SCIs, the timer counter, the RTI, and COP. See Table 11-3. MCLK is the module clock and PCLK is an internal bus rate clock. Table 11-3. Module Clock Selection MCS[B:A] 00 01 10 11 MCLK PCLK PCLK -------------2 PCLK -------------4 PCLK -------------8 The BCSx and MCSx bits can be changed with a single-write access. In combination, these bits can be used to "throttle" the CPU clock rate without affecting the MCLK rate; timing and baud rates can remain constant as the processor speed is changed to match system requirements. This can save overall system power. MC68HC812A4 -- Rev. 3.0 174 Phase-Lock Loop (PLL) Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 12. Standard Timer Module 12.1 Contents 12.2 12.3 12.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.5.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 12.5.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 12.5.4.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .185 12.5.4.2 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . .185 12.6 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .186 12.6.1 Timer IC/OC Select Register . . . . . . . . . . . . . . . . . . . . . . .186 12.6.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . .187 12.6.3 Timer Output Compare 7 Mask Register . . . . . . . . . . . . . .187 12.6.4 Timer Output Compare 7 Data Register. . . . . . . . . . . . . . .188 12.6.5 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . .189 12.6.6 Timer System Control Register . . . . . . . . . . . . . . . . . . . . .190 12.6.7 Timer Control Registers 1 and 2 . . . . . . . . . . . . . . . . . . . .192 12.6.8 Timer Control Registers 3 and 4 . . . . . . . . . . . . . . . . . . . .193 12.6.9 Timer Mask Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 12.6.10 Timer Mask Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 12.6.11 Timer Flag Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 12.6.12 Timer Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 12.6.13 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .197 12.6.14 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . .198 12.6.15 Pulse Accumulator Flag Register . . . . . . . . . . . . . . . . . . . .200 12.6.16 Pulse Accumulator Counter Registers . . . . . . . . . . . . . . . .201 12.6.17 Timer Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 175 Standard Timer Module 12.7 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 12.7.1 Input Capture/Output Compare Pins . . . . . . . . . . . . . . . . .203 12.7.2 Pulse Accumulator Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 12.8 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 12.9 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 12.9.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 12.9.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 12.9.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.10 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.11 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.11.1 Timer Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.11.2 Timer Port Data Direction Register . . . . . . . . . . . . . . . . . .207 12.11.3 Data Direction Register for Timer Port . . . . . . . . . . . . . . . .208 12.12 Using the Output Compare Function to Generate a Square Wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 12.12.1 Sample Calculation to Obtain Period Counts . . . . . . . . . . .209 12.12.2 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12.12.3 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12.2 Introduction The standard timer module is a 16-bit, 8-channel timer with: * * * Input capture Output compare Pulse accumulator functions A block diagram is given in Figure 12-1 and a summary of the input/oputput (I/O) registers is shown in Figure 12-2. MC68HC812A4 -- Rev. 3.0 176 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Block Diagram 12.3 Block Diagram CLK[1:0] PR[2:1:0] MODULE CLOCK PACLK PACLK/256 PACLK/65536 CHANNEL 7 OUTPUT COMPARE MUX TCRE PRESCALER CxI CxF CLEAR COUNTER 16-BIT COUNTER TE CHANNEL 0 16-BIT COMPARATOR TIMC0H:TIMC0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TIMC1H:TIMC1L 16-BIT LATCH EDG1A EDG1B CHANNELS 2-6 CHANNEL 7 16-BIT COMPARATOR TIMC7H:TIMC7L 16-BIT LATCH EDG7A EDG7B C7F EDGE DETECT C1F EDGE DETECT EDG0A EDG0B C0F EDGE DETECT TOF TOI TIMCNTH:TIMCNTL INTERRUPT LOGIC INTERRUPT REQUEST IOS0 OM0 OL0 PT0 LOGIC CH. 0 CAPTURE CH. 0 COMPARE PAD IOS1 OM1 OL1 PT1 LOGIC CH. 1 CAPTURE CH. 1 COMPARE PAD IOS7 OM7 OL7 PEDGE PT7 LOGIC CH. 7 CAPTURE PA INPUT CH. 7 COMPARE PAD PAOVF TIMPACNTH:TIMPACNTL PAE EDGE DETECT PACLK/65536 PACLK/256 INTERRUPT REQUEST PAOVI PAOVF 16-BIT COUNTER PACLK PAMOD INTERRUPT LOGIC DIVIDE-BY-64 PAI PAIF MODULE CLOCK PAIF Figure 12-1. Timer Block Diagram Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 177 Standard Timer Module 12.4 Register Map NOTE: The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Bit 7 Read: Write: Reset: Read: Write: Reset: IOS7 0 FOC7 0 6 IOS6 0 FOC6 0 OC7M6 0 OC7D6 0 14 5 IOS5 0 FOC5 0 OC7M5 0 OC7D5 0 13 4 IOS4 0 FOC4 0 OC7M4 0 OC7D4 0 12 3 IOS3 0 FOC3 0 OC7M3 0 OC7D3 0 11 2 IOS2 0 FOC2 0 OC7M2 0 OC7D2 0 10 1 IOS1 0 FOC1 0 OC7M1 0 OC7D1 0 9 Bit 0 IOS0 0 FOC0 0 OC7M0 0 OC7D0 0 Bit 8 Addr. Register Name Timer IC/OC Select Register (TIOS) See page 186. Timer Compare Force Register (CFORC) See page 187. $0080 $0081 $0082 Timer Output Read: OC7M7 Compare 7 Mask Write: Register (OC7M) See page 187. Reset: 0 Timer Output Read: Compare 7 Data Write: Register (OC7D) See page 188. Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: 0 TEN 0 R 0 Bit 7 OC7D7 0 Bit 15 $0083 Timer Counter Register $0084 High (TCNTH) See page 189. Timer Counter Register $0085 Low (TCNTL) See page 189. Timer System Control Register (TSCR) See page 190. Reserved 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 TSWAI 0 R 0 TSBCK 0 R 0 TFFCA 0 R R 0 0 0 0 0 0 0 0 $0086 0 R = Rserved 0 R 0 R 0 R $0087 = Unimplemented Figure 12-2. I/O Register Summary (Sheet 1 of 5) MC68HC812A4 -- Rev. 3.0 178 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Register Map Addr. Register Name Timer Control Register 1 (TCTL1) See page 192. Timer Control Register 2 (TCTL2) See page 192. Timer Control Register 3 (TCTL3) See page 193. Timer Control Register 4 (TCTL4) See page 193. Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 OM7 0 OM3 0 EDG7B 0 EDG3B 0 C7I 0 TOI 0 C7F 0 TOF 0 Bit 15 0 Bit 7 0 6 OL7 0 OL3 0 EDG7A 0 EDG3A 0 C6I 0 0 5 OM6 0 OM2 0 EDG6B 0 EDG2B 0 C5I 0 PUPT 1 C5F 0 0 4 OL6 0 OL2 0 EDG6A 0 EDG2A 0 C4I 0 RDPT 1 C4F 0 0 3 OM5 0 OM1 0 EDG5B 0 EDG1B 0 C3I 0 TCRE 0 C3F 0 0 2 OL5 0 OL1 0 EDG5A 0 EDG1A 0 C2I 0 PR2 0 C2F 0 0 1 OM4 0 OM0 0 EDG4B 0 EDG0B 0 C1I 0 PR1 0 C1F 0 0 Bit 0 OL4 0 OL0 0 EDG4A 0 EDG0A 0 C0I 0 PR0 0 C0F 0 0 $0088 $0089 $008A $008B Timer Mask Register 1 $008C (TMSK1) See page 194. Timer Mask Register 2 $008D (TMSK2) See page 194. Timer Flag Register 1 (TFLG1) See page 196. Timer Flag Register 2 (TFLG2) See page 196. Timer Channel 0 Register High (TC0H) See page 197. Timer Channel 0 Register Low (TC0L) See page 197. 0 C6F 0 0 $008E $008F 0 14 0 6 0 0 13 0 5 0 0 12 0 4 0 R 0 11 0 3 0 = Rserved 0 10 0 2 0 0 9 0 1 0 0 Bit 8 0 Bit 0 0 $0090 $0091 = Unimplemented Figure 12-2. I/O Register Summary (Sheet 2 of 5) Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 179 Standard Timer Module Addr. Register Name Timer Channel 1 Register High (TC1H) See page 197. Timer Channel 1 Register Low (TC1L) See page 197. Timer Channel 2 Register High (TC2H) See page 197. Timer Channel 2 Register Low (TC2L) See page 197. Timer Channel 3 Register High (TC3H) See page 197. Timer Channel 3 Register Low (TC3L) See page 197. Timer Channel 4 Register High (TC4H) See page 197. Timer Channel 4 Register Low (TC4L) See page 197. Timer Channel 5 Register High (TC5H) See page 197. Timer Channel 5 Register Low (TC5L) See page 197. Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 6 14 0 6 0 14 0 6 0 14 0 6 0 14 0 6 0 14 0 6 0 5 13 0 5 0 13 0 5 0 13 0 5 0 13 0 5 0 13 0 5 0 4 12 0 4 0 12 0 4 0 12 0 4 0 12 0 4 0 12 0 4 0 R 3 11 0 3 0 11 0 3 0 11 0 3 0 11 0 3 0 11 0 3 0 = Rserved 2 10 0 2 0 10 0 2 0 10 0 2 0 10 0 2 0 10 0 2 0 1 9 0 1 0 9 0 1 0 9 0 1 0 9 0 1 0 9 0 1 0 Bit 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B = Unimplemented Figure 12-2. I/O Register Summary (Sheet 3 of 5) MC68HC812A4 -- Rev. 3.0 180 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Register Map Addr. Register Name Timer Channel 6 Register High (TC6H) See page 197. Timer Channel 6 Register Low (TC6L) See page 197. Timer Channel 7 Register High (TC7H) See page 197. Timer Channel 7 Register Low (TC7L) See page 197. Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 Bit 15 0 Bit 7 0 Bit 15 0 Bit 7 0 0 6 14 0 6 0 14 0 6 0 PAEN 0 0 5 13 0 5 0 13 0 5 0 PAMOD 0 0 4 12 0 4 0 12 0 4 0 PEDGE 0 0 3 11 0 3 0 11 0 3 0 CLK1 0 0 2 10 0 2 0 10 0 2 0 CLK0 0 0 1 9 0 1 0 9 0 1 0 PAOVI 0 PAOVF 0 9 0 1 0 TCBYP Bit 0 Bit 8 0 Bit 0 0 Bit 8 0 0 0 PAI 0 PAIF 0 Bit 8 0 Bit 0 0 PCBYP $009C $009D $009E $009F $00A0 Pulse Accumulator Read: Control Register Write: (PACTL) See page 198. Reset: Read: Write: Reset: 0 0 Pulse Accumulator Flag $00A1 Register (PAFLG) See page 200. 0 Bit 15 0 Bit 7 0 0 0 14 0 6 0 0 0 13 0 5 0 0 0 12 0 4 0 0 0 11 0 3 0 0 0 10 0 2 0 0 $00A2 Pulse Accumulator Read: Counter Register High Write: (PACNTH) See page 201. Reset: Pulse Accumulator Read: Counter Register Low Write: (PACNTL) See page 201. Reset: Timer Test Register (TIMTST) See page 202. Read: Write: Reset: $00A3 $00AD 0 0 0 0 R 0 = Rserved 0 0 0 = Unimplemented Figure 12-2. I/O Register Summary (Sheet 4 of 5) Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 181 Standard Timer Module Addr. Register Name Timer Port Data Register (PORTT) See page 206. Read: Write: Reset: Bit 7 PT7 6 PT6 5 PT5 4 PT4 3 PT3 2 PT2 1 PT1 Bit 0 PT0 $00AE Unaffected by reset Bit 7 0 5 0 5 0 4 0 R 3 0 = Rserved 2 0 1 0 Bit 0 0 $00AF Timer Port Data Read: Direction Register Write: (DDRT) See page 207. Reset: = Unimplemented Figure 12-2. I/O Register Summary (Sheet 5 of 5) NOTE: In normal modes, writing to a reserved bit has no effect and reading returns logic 0. In any mode, writing to an unimplemented bit has no effect and reading returns a logic 0. 12.5 Functional Description This section provides a functional description of the standard timer. 12.5.1 Prescaler The prescaler divides the module clock by 1, 2, 4, 8, 16, 32, 64, or 128. The prescaler select bits, PR2, PR1, and PR0, select the prescaler divisor. PR2, PR1, and PR0 are in timer system control register 2 (TIMSCR2). 12.5.2 Input Capture Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TIMCxH and TIMCxL. MC68HC812A4 -- Rev. 3.0 182 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Functional Description In 8-bit MCUs, the low byte of the timer channel register (TIMCxL) is held for one bus cycle after the high byte (TIMCxH) is read. This allows coherent reading of the timer channel such that an input capture does not occur between two back-to-back 8-bit reads. To read the 16-bit timer channel register, use a double-byte read instruction such as LDD or LDX. The minimum pulse width for the input capture input is greater than two module clocks. The input capture function does not force data direction. The timer port data direction register controls the data direction of an input capture pin. Pin conditions can trigger an input capture on a pin configured as an input. Software can trigger an input capture on an input capture pin configured as an output. An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. 12.5.3 Output Compare Setting the I/O select bit, IOSx, configures channel x as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. The output mode and level bits, OMx and OLx, select set, clear, or toggle on output compare. Clearing both OMx and OLx disconnects the pin from the output logic. Setting a force output compare bit, FOCx, causes an immediate output compare on channel x. A forced output compare does not set the channel flag. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 183 Standard Timer Module An output compare on channel 7 overrides output compares on all other output compare channels. A channel 7 output compare causes any unmasked bits in the output compare 7 data register to transfer to the timer port data register. The output compare 7 mask register masks the bits in the output compare 7 data register. The timer counter reset enable bit, TCRE, enables channel 7 output compares to reset the timer counter. A channel 7 output compare can reset the timer counter even if the OC7/PAI pin is being used as the pulse accumulator input. An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. 12.5.4 Pulse Accumulator The pulse accumulator (PA) is a 16-bit counter that can operate in two modes: * * Event counter mode -- Counting edges of selected polarity on the pulse accumulator input pin, PAI Gated time accumulation mode -- Counting pulses from a divide-by-64 clock The PA mode bit, PAMOD, selects the mode of operation. The minimum pulse width for the PAI input is greater than two module clocks. MC68HC812A4 -- Rev. 3.0 184 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Functional Description 12.5.4.1 Event Counter Mode Clearing the PAMOD bit configures the PA for event counter operation. An active edge on the PAI pin increments the PA. The PA edge bit, PEDGE, selects falling edges or rising edges to increment the PA. An active edge on the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to generate interrupt requests. NOTE: The PAI input and timer channel 7 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare 7 mask bit, OC7M7. The PA counter registers, TIMPACNTH/L, reflect the number of active input edges on the PAI pin since the last reset. The PA overflow flag, PAOVF, is set when the PA rolls over from $FFFF to $0000. The PA overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. NOTE: The PA can operate in event counter mode even when the timer enable bit, TE, is clear. 12.5.4.2 Gated Time Accumulation Mode Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the PAI pin enables a divided-by-64 clock to drive the PA. The PA edge bit, PEDGE, selects low levels or high levels to enable the divided-by-64 clock. The trailing edge of the active level at the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to generate interrupt requests. NOTE: The PAI input and timer channel 7 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare mask bit, OC7M7. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 185 Standard Timer Module The PA counter registers, TIMPACNTH/L reflect the number of pulses from the divided-by-64 clock since the last reset. NOTE: The timer prescaler generates the divided-by-64 clock. If the timer is not active, there is no divided-by-64 clock. PULSE ACCUMULATOR PAD CHANNEL 7 OUTPUT COMPARE OM7 OL7 OC7M7 Figure 12-3. Channel 7 Output Compare/Pulse Accumulator Logic 12.6 Registers and Reset Initialization This section describes the registers and reset initialization. 12.6.1 Timer IC/OC Select Register Address: $0080 Bit 7 Read: Write: Reset: IOS7 0 6 IOS6 0 5 IOS5 0 4 IOS4 0 3 IOS3 0 2 IOS2 0 1 IOS1 0 Bit 0 IOS0 0 Figure 12-4. Timer IC/OC Select Register (TIOS) Read: Anytime Write: Anytime IOS7-IOS0 -- Input Capture or Output Compare Select Bits The IOSx bits enable input capture or output compare operation for the corresponding timer channel. 1 = Output compare enabled 0 = Input capture enabled MC68HC812A4 -- Rev. 3.0 186 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization 12.6.2 Timer Compare Force Register Address: $0081 Bit 7 Read: Write: Reset: FOC7 0 6 FOC6 0 5 FOC5 0 4 FOC4 0 3 FOC3 0 2 FOC2 0 1 FOC1 0 Bit 0 FOC0 0 Figure 12-5. Timer Compare Force Register (CFORC) Read: Anytime; always read $00 (1 state is transient) Write: Anytime FOC7-FOC0 -- Force Output Compare Bits Setting an FOCx bit causes an immediate output compare on the corresponding channel. Forcing an output compare does not set the output compare flag. 1 = Force output compare 0 = No effect 12.6.3 Timer Output Compare 7 Mask Register Address: $0082 Bit 7 Read: Write: Reset: OC7M7 0 6 OC7M6 0 5 OC7M5 0 4 OC7M4 0 3 OC7M3 0 2 OC7M2 0 1 OC7M1 0 Bit 0 OC7M0 0 Figure 12-6. Timer Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime OC7M7-OC7M0 -- Output Compare 7 Mask Bits Setting an OC7Mx bit configures the corresponding TIMPORT pin to be an output. OC7Mx makes the timer port pin an output regardless of the data direction bit when the pin is configured for output compare (IOSx = 1). The OC7Mx bits do not change the state of the TIMDDR bits. 1 = Corresponding TIMPORT pin output 0 = Corresponding TIMPORT pin input Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 187 Standard Timer Module 12.6.4 Timer Output Compare 7 Data Register Address: $0083 Bit 7 Read: OC7D7 Write: Reset: 0 0 0 0 0 0 0 0 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 6 5 4 3 2 1 Bit 0 Figure 12-7. Timer Output Compare 7 Data Register (OC7D) Read: Anytime Write: Anytime OC7D7-OC7D0 -- Output Compare Data Bits When a successful channel 7 output compare occurs, these bits transfer to the timer port data register if the corresponding OC7Mx bits are set. NOTE: A successful channel 7 output compare overrides any channel 0-6 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit. MC68HC812A4 -- Rev. 3.0 188 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization 12.6.5 Timer Counter Registers Address: $0084 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 = Unimplemented Figure 12-8. Timer Counter Register High (TCNTH) Address: $0085 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 = Unimplemented Figure 12-9. Timer Counter Register Low (TCNTL) Read: Anytime Write: Only in special modes; has no effect in normal modes Use a double-byte read instruction to read the timer counter. Two single-byte reads return a different value than a double-byte read. NOTE: The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 189 Standard Timer Module 12.6.6 Timer System Control Register Address: $0086 Bit 7 Read: TEN Write: Reset: 0 0 0 0 0 0 0 0 TSWAI TSBCK TFFCA 6 5 4 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 12-10. Timer System Control Register (TSCR) Read: Anytime Write: Anytime TEN -- Timer Enable Bit TEN enables the timer. Clearing TEN reduces power consumption. 1 = Timer enabled 0 = Timer and timer counter disabled When the timer is disabled, there is no divided-by-64 clock for the PA since the prescaler generates the M / 64 clock. TSWAI -- Timer Stop in Wait Mode Bit TSWAI disables the timer and PA in wait mode. 1 = Timer and PA disabled in wait mode 0 = Timer and PA enabled in wait mode NOTE: If timer and PA interrupt requests are needed to bring the MCU out of wait mode, clear TSWAI before executing the WAIT instruction. TSBCK -- Timer Stop in Background Mode Bit TSBCK stops the timer during background mode. 1 = Timer disabled in background mode 0 = Timer enabled in background mode NOTE: Setting TSBCK does not stop the PA when it is in event counter mode. MC68HC812A4 -- Rev. 3.0 190 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization TFFCA -- Timer Fast Flag Clear-All Bit When TFFCA is set: - An input capture read or a write to an output compare channel clears the corresponding channel flag, CnF. - Any access of the timer counter registers, TCNTH/L, clears the TOF flag. - Any access of the PA counter registers, PACNTH/L, clears both the PAOVF and PAIF flags in the PAFLG register. When TFFCA is clear, writing logic 1s to the flags clears them. 1 = Fast flag clearing 0 = Normal flag clearing WRITE TFLG1 REGISTER DATA BIT n CnF CLEAR CnF FLAG TFFCA READ TCx REGISTERS WRITE TCx REGISTERS Figure 12-11. Fast Clear Flag Logic Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 191 Standard Timer Module 12.6.7 Timer Control Registers 1 and 2 Address: $0088 Bit 7 Read: Write: Reset: OM7 0 6 OL7 0 5 OM6 0 4 OL6 0 3 OM5 0 2 OL5 0 1 OM4 0 Bit 0 OL4 0 Figure 12-12. Timer Control Register 1 (TCTL1) Address: $0089 Bit 7 Read: Write: Reset: OM3 0 6 OL3 0 5 OM2 0 4 OL2 0 3 OM1 0 2 OL1 0 1 OM0 0 Bit 0 OL0 0 Figure 12-13. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime OMx/OLx -- Output Mode/Output Level Bits These bit pairs select the output action to be taken as a result of a successful output compare. When either OMx or OLx is set and the IOSx bit is set, the pin is an output regardless of the state of the corresponding DDRT bit. Table 12-1. Selection of Output Compare Action OMx:OLx 00 01 10 11 Action on Output Compare Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line Set OCn output line Channel 7 shares a pin with the pulse accumulator input pin. To use the PAI input, clear both the OM7 and OL7 bits and clear the OC7M7 bit in the output compare 7 mask register. MC68HC812A4 -- Rev. 3.0 192 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization 12.6.8 Timer Control Registers 3 and 4 Address: $008A Bit 7 Read: EDG7B Write: Reset: 0 0 0 0 0 0 0 0 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 6 5 4 3 2 1 Bit 0 Figure 12-14. Timer Control Register 3 (TCTL3) Address: $008B Bit 7 Read: EDG3B Write: Reset: 0 0 0 0 0 0 0 0 EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 6 5 4 3 2 1 Bit 0 Figure 12-15. Timer Control Register 4 (TCTL4) Read: Anytime Write: Anytime EDGnB, EDGnA -- Input Capture Edge Control Bits These eight bit pairs configure the input capture edge detector circuits. Table 12-2. Input Capture Edge Selection EDGnB:EDGnA 00 01 10 11 Edge Selection Input capture disabled Input capture on rising edges only Input capture on falling edges only Input capture on any edge (rising or falling) Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 193 Standard Timer Module 12.6.9 Timer Mask Register 1 Address: $008C Bit 7 Read: C7I Write: Reset: 0 0 0 0 0 0 0 0 C6I C5I C4I C3I C2I C1I C0I 6 5 4 3 2 1 Bit 0 Figure 12-16. Timer Mask 1 Register (TMSK1) Read: Anytime Write: Anytime C7I-C0I -- Channel Interrupt Enable Bits These bits enable the flags in timer flag register 1. 1 = Corresponding channel interrupt requests enabled 0 = Corresponding channel interrupt requests disabled 12.6.10 Timer Mask Register 2 Address: $008D Bit 7 Read: TOI Write: Reset: 0 0 1 1 0 0 0 0 6 0 PUPT RDPT TCRE PR2 PR1 PR0 5 4 3 2 1 Bit 0 = Unimplemented Figure 12-17. Timer Mask 2 Register (TMSK2) Read: Anytime Write: Anytime TOI -- Timer Overflow Interrupt Enable Bit TOI enables interrupt requests generated by the TOF flag. 1 = TOF interrupt requests enabled 0 = TOF interrupt requests disabled MC68HC812A4 -- Rev. 3.0 194 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization PUPT -- Port T Pullup Enable Bit PUPT enables pullup resistors on the timer port pins when the pins are configured as inputs. 1 = Pullup resistors enabled 0 = Pullup resistors disabled RDPT -- Port T Reduced Drive Bit RDPT reduces the output driver size for lower current and less noise. 1 = Output drive reduction enabled 0 = Output drive reduction disabled TCRE -- Timer Counter Reset Enable Bit TCRE allows the counter to be reset by a channel 7 output compare. 1 = Counter reset enabled 0 = Counter reset disabled NOTE: When the timer channel 7 registers contain $0000 and TCRE is set, the timer counter registers remain at $0000 all the time. When the timer channel 7 registers contain $FFFF and TCRE is set, TOF never gets set even though the timer counter registers go from $FFFF to $0000. PR2, PR1, and PR0 -- Timer Prescaler Select Bits These bits select the prescaler divisor for the timer counter. Table 12-3. Prescaler Selection PR[2:1:0] 000 001 010 011 100 101 110 111 Prescaler Divisor 1 2 4 8 16 32 Reserved Reserved NOTE: The newly selected prescale divisor does not take effect until the next synchronized edge when all prescale counter stages equal 0. MC68HC812A4 -- Rev. 3.0 Standard Timer Module 195 Advance Information MOTOROLA Standard Timer Module 12.6.11 Timer Flag Register 1 Address: $008E Bit 7 Read: C7F Write: Reset: 0 0 0 0 0 0 0 0 C6F C5F C4F C3F C2F C1F C0F 6 5 4 3 2 1 Bit 0 Figure 12-18. Timer Flag Register 1 (TFLG1) Read: Anytime Write: Anytime; writing 1 clears flag; writing 0 has no effect C7F-C0F -- Channel Flags These flags are set when an input capture or output compare occurs on the corresponding channel. Clear a channel flag by writing a 1 to it. NOTE: When the fast flag clear-all bit, TFFCA, is set, an input capture read or an output compare write clears the corresponding channel flag. TFFCA is in the timer system control register (TSCR). 12.6.12 Timer Flag Register 2 Address: $008F Bit 7 Read: TOF Write: Reset: 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 12-19. Timer Flag Register 2 (TFLG2) Read: Anytime Write: Anytime; writing 1 clears flag; writing 0 has no effect MC68HC812A4 -- Rev. 3.0 196 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization TOF -- Timer Overflow Flag TOF is set when the timer counter rolls over from $FFFF to $0000. Clear TOF by writing a 1 to it. 1 = Timer overflow 0 = No timer overflow NOTE: When the timer channel 7 registers contain $FFFF and the timer counter reset enable bit, TCRE, is set, TOF does not get set when the counter rolls over. When the fast flag clear-all bit, TFFCA, is set, any access to the timer counter registers clears TOF. NOTE: 12.6.13 Timer Channel Registers TC0H/L: $0090/$0091 TC1H/L: $0092/$0093 TC2H/L: $0094/$0095 TC3H/L: $0096/$0097 TC4H/L: $0098/$0099 TC5H/L: $009A/$009B TC6H/L: $009C/$009D TC7H/L: $009E/$009F Bit 7 Read: Bit 15 Write: Reset: 0 Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 14 13 12 11 10 9 8 6 5 4 3 2 1 Bit 0 Figure 12-20. Timer Channel Registers (TCxH/L) Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 197 Standard Timer Module Read: Anytime Write: Output compare channel, anytime; input capture channel, no effect When a channel is configured for input capture (IOSx = 0), the timer channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin. When a channel is configured for output compare (IOSx = 1), the timer channel registers contain the output compare value. 12.6.14 Pulse Accumulator Control Register Address: $00A0 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 12-21. Pulse Accumulator Control Register (PACTL) Read: Anytime Write: Anytime PAEN -- Pulse Accumulator Enable Bit PAEN enables the pulse accumulator. 1 = Pulse accumulator enabled 0 = Pulse accumulator disabled NOTE: The pulse accumulator can operate even when the timer enable bit, TEN, is clear. PAMOD -- Pulse Accumulator Mode Bit PAMOD selects event counter mode or gated time accumulation mode. 1 = Gated time accumulation mode 0 = Event counter mode MC68HC812A4 -- Rev. 3.0 198 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization PEDGE -- Pulse Accumulator Edge Bit PEDGE selects falling or rising edges on the PAI pin to increment the counter. In event counter mode (PAMOD = 0): 1 = Rising PAI edge increments counter 0 = Falling PAI edge increments counter In gated time accumulation mode (PAMOD = 1): 1 = Low PAI input enables divided-by-64 clock to pulse accumulator and trailing rising edge on PAI sets PAIF flag 0 = High PAI input enables divided-by-64 clock to pulse accumulator and trailing falling edge on PAI sets PAIF flag NOTE: The timer prescaler generates the divided-by-64 clock. If the timer is not active, there is no divided-by-64 clock. To operate in gated time accumulation mode: 1. Apply logic 0 to the RESET pin. 2. Initialize registers for pulse accumulator mode test. 3. Apply appropriate level on PAI pin. 4. Enable the timer. CLK1 and CLK0 -- Clock Select Bits CLK1 and CLK0 select the timer counter input clock as shown in Table 12-4. Table 12-4. Clock Selection CLK[1:0] 00 01 10 Timer Counter Clock(1) Timer prescaler clock(2) PACLK PACLK -----------------256 PACLK -----------------65,536 11 1. Changing the CLKx bits causes an immediate change in the timer counter clock input. 2. When PAE = 0, the timer prescaler clock is always the timer counter clock. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 199 Standard Timer Module PAOVI -- Pulse Accumulator Overflow Interrupt Enable Bit PAOVI enables the pulse accumulator overflow flag, PAOVF, to generate interrupt requests. 1 = PAOVF interrupt requests enabled 0 = PAOVF interrupt requests disabled PAI -- Pulse Accumulator Interrupt Enable Bit PAI enables the pulse accumulator input flag, PAIF, to generate interrupt requests. 1 = PAIF interrupt requests enabled 0 = PAIF interrupt requests disabled 12.6.15 Pulse Accumulator Flag Register Address: $00A1 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 PAOVF PAIF 1 Bit 0 = Unimplemented Figure 12-22. Pulse Accumulator Flag Register (PAFLG) Read: Anytime Write: Anytime; writing 1 clears the flag; writing 0 has no effect PAOVF -- Pulse Accumulator Overflow Flag PAOVF is set when the 16-bit pulse accumulator overflows from $FFFF to $0000. Clear PAOVF by writing to the pulse accumulator flag register with PAOVF set. 1 = Pulse accumulator overflow 0 = No pulse accumulator overflow MC68HC812A4 -- Rev. 3.0 200 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Registers and Reset Initialization PAIF -- Pulse Accumulator Input Flag PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. Clear PAIF by writing to the pulse accumulator flag register with PAIF set. 1 = Active PAI input 0 = No active PAI input NOTE: When the fast flag clear-all enable bit, TFFCA, is set, any access to the pulse accumulator counter registers clears all the flags in the PAFLG register. 12.6.16 Pulse Accumulator Counter Registers Address: $00A2 Bit 7 Read: Bit 15 Write: Reset: 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0 Address: $00A3 Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 12-23. Pulse Accumulator Counter Registers (PACNTH/L) Read: Anytime Write: Anytime These registers contain the number of active input edges on the PAI pin since the last reset. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 201 Standard Timer Module Use a double-byte read instruction to read the pulse accumulator counter. Two single-byte reads return a different value than a double-byte read. NOTE: Reading the pulse accumulator counter registers immediately after an active edge on the PAI pin may miss the last count since the input has to be synchronized with the bus clock first. 12.6.17 Timer Test Register Address: $00AD Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 TCBYP Bit 0 PCBYP = Unimplemented Figure 12-24. Timer Test Register (TIMTST) Read: Anytime Write: Only in special mode (SMODN = 0) TCBYP -- Timer Divider Chain Bypass Bit TCBYP divides the 16-bit free-running timer counter into two 8-bit halves. The clock drives both halves directly and bypasses the timer prescaler. 1 = Timer counter divided in half and prescaler bypassed 0 = Normal operation PCBYP -- Pulse Accumulator Divider Chain Bypass Bit PCBYP divides the 16-bit PA counter into two 8-bit halves. The clock drives both halves directly and bypasses the timer prescaler. 1 = PA counter divided in half and prescaler bypassed 0 = Normal operation MC68HC812A4 -- Rev. 3.0 202 Standard Timer Module Advance Information MOTOROLA Standard Timer Module External Pins 12.7 External Pins The timer has eight pins for input capture and output compare functions. One of the pins is also the pulse accumulator input. All eight pins are available for general-purpose I/O when not configured for timer functions. 12.7.1 Input Capture/Output Compare Pins The IOSx bits in the timer IC/OC select register configure the timer port pins as either output compare or input capture pins. The timer port data direction register controls the data direction of an input capture pin. External pin conditions trigger input captures on input capture pins configured as inputs. Software triggers input captures on input capture pins configured as outputs. The timer port data direction register does not affect the data direction of an output compare pin. The output compare function overrides the data direction register but does not affect the state of the data direction register. 12.7.2 Pulse Accumulator Pin Setting the PAE bit in the pulse accumulator control register enables the pulse accumulator input pin, PAI. NOTE: The PAI input and timer channel 7 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare mask bit, OC7M7. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 203 Standard Timer Module 12.8 Background Debug Mode If the TSBCK bit is clear, background debug mode has no effect on the timer. If TSBCK is set, background debug mode disables the timer. NOTE: Setting TSBCK does not stop the pulse accumulator when it is in event counter mode. 12.9 Low-Power Options This section describes the three low-power modes: * * * Run mode Wait mode Stop mode 12.9.1 Run Mode Clearing the timer enable bit (TEN) or the pulse accumulator enable bit (PAEN) reduces power consumption in run mode. TEN is in the timer system control register (TSCR). PAEN is in the pulse accumulator control register (PACTL). Timer and pulse accumulator registers are still accessible, but clocks to the core of the timer are disabled. 12.9.2 Wait Mode Timer and pulse accumulator operation in wait mode depend on the state of the TSWAI bit in the timer system control register TSCR). * * If TSWAI is clear, the timer and pulse accumulator operate normally when the CPU is in wait mode. If TSWAI is set, timer and pulse accumulator clock generation ceases and the TIM module enters a power-conservation state when the CPU is in wait mode. In this condition, timer and pulse accumulator registers are not accessible. Setting TSWAI does not affect the state of the timer enable bit, TEN, or the pulse accumulator enable bit, PAEN. Advance Information Standard Timer Module MOTOROLA MC68HC812A4 -- Rev. 3.0 204 Standard Timer Module Interrupt Sources 12.9.3 Stop Mode The STOP instruction disables the timer for reduced power consumption. 12.10 Interrupt Sources Table 12-5. Timer Interrupt Sources Interrupt Source Timer channel 0 Timer channel 1 Timer channel 2 Timer channel 3 Timer channel 4 Timer channel 5 Timer channel 6 Timer channel 7 Timer overflow Pulse accumulator overflow Pulse accumulator input Flag C0F C1F C2F C3F C4F C5F C6F C7F TOF PAOVF PAIF Local Enable C0I C1I C2I C3I C4I C5I C6I C7I TOI PAOVI PAI CCR Mask I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit Vector Address $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB 12.11 General-Purpose I/O Ports This section describes the general-purpose I/O ports. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 205 Standard Timer Module 12.11.1 Timer Port Data Register An I/O pin used by the timer defaults to general-purpose I/O unless an internal function which uses that pin is enabled. Address: $00AE Bit 7 Read: PT7 Write: Reset: Timer function: PA function: IC/OC7 PAI IC/OC6 IC/OC5 Unaffected by reset IC4OC4 IC/OC3 IC/OC2 IC/OC1 IC/OC0 PT6 PT5 PT4 PT3 PT2 PT1 PT0 6 5 4 3 2 1 Bit 0 Figure 12-25. Timer Port Data Register (PORTT) Read: Anytime Write: Anytime PT7-PT0 -- Timer Port Data Bits Data written to PORTT is buffered and drives the pins only when they are configured as general-purpose outputs. Reading an input (data direction bit = 0) reads the pin state; reading an output (data direction bit = 1) reads the latch. Writing to a pin configured as a timer output does not change the pin state. NOTE: Due to input synchronizer circuitry, the minimum pulse width for a pulse accumulator input or an input capture input should always be greater than the width of two module clocks. Table 12-6. TIMPORT I/O Function In Data Direction Register 0 0 1 1 Output Compare Action 0 1 1 0 Reading at Data Bus Pin Pin Port data register Port data register Out Reading at Pin Pin Output compare action Output compare action Port data register Advance Information Standard Timer Module MOTOROLA MC68HC812A4 -- Rev. 3.0 206 Standard Timer Module General-Purpose I/O Ports 12.11.2 Timer Port Data Direction Register Address: $00AF Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 12-26. Timer Port Data Direction Register (DDRT) Read: Anytime Write: Anytime Bits 7-0 -- TIMPORT Data Direction Bits These bits control the port logic of PORTT. Reset clears the timer port data direction register, configuring all timer port pins as inputs. 1 = Corresponding pin configured as output 0 = Corresponding pin configured as input NOTE: By setting the IOSx bit input capture configuration no matter what the state of the data direction register is, the timer forces output compare pins to be outputs and input capture pins to be inputs. Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 207 Standard Timer Module 12.11.3 Data Direction Register for Timer Port Address: $00AF Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 Bit 5 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 12-27. Data Direction Register for Timer Port (DDRT) Read: Anytime Write: Anytime Bits 7-0 -- DDRT Data Direction Bits 0 = Configures the corresponding I/O pin for input only 1 = Configures the corresponding I/O pin for output The timer forces the I/O state to be an output for each timer port pin associated with an enabled output compare. In these cases, the data direction bits do not change but have no effect on the direction of these pins. The DDRT reverts to controlling the I/O direction of a pin when the associated timer output compare is disabled. Input captures do not override the DDRT settings. MC68HC812A4 -- Rev. 3.0 208 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Using the Output Compare Function to Generate a Square Wave 12.12 Using the Output Compare Function to Generate a Square Wave This timer exercise is intended to utilize the output compare function to generate a square wave of predetermined duty cycle and frequency. Square wave frequency 1000 Hz, duty cycle 50% The program generates a square wave, 50 percent duty cycle, on output compare 2 (OC2). The signal will be measured by the HC11 on the UDLP1 board. It assumes a 8.0 MHz operating frequency for the E clock. The control registers are initialized to disable interrupts, configure for proper pin control action and also the TC2H register for desired compare value. The appropiate count must be calculated to achieve the desired frequency and duty cycle. For example: for a 50 percent duty, 1 KHz signal each period must consist of 2048 counts or 1024 counts high and 1024 counts low. In essence a $0400 is added to generate a frequency of 1 kHz. 12.12.1 Sample Calculation to Obtain Period Counts The sample calculation to obtain period counts is: * For 1000 Hz frequency: - E-clock = 8 MHz - IC/OC resolution factor = 1/(E-clock/Prescaler) - If the Prescaler = 4, then output compare resolution is 0.5 s * For a 1 KHz, 50 percent duty cycle: - 1/F = T = 1/1000 = 1 ms - F for output compare = prescaler/E clock = 2 MHz 1 ms NUMBER OF CLOCKS = F * D THEREFORE, #CLOCKS = (2 MHz) * (0.5 ms) = 1024 = $0400 0.5 ms Figure 12-28. Example Waveform Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 209 Standard Timer Module 12.12.2 Equipment For this exercise, use the M68HC812A4EVB emulation board. 12.12.3 Code Listing NOTE: A comment line is deliminted by a semi-colon. If there is no code before comment, an ";" must be placed in the first column to avoid assembly errors. ---------------------------------------------------------------------; MAIN PROGRAM ; ---------------------------------------------------------------------ORG $7000 ; 16K On-Board RAM, User code data area, ; ; start main program at $7000 MAIN: BSR TIMERINIT ; Subroutine used to initialize the timer: ; ; Output compare channel, no interrupts BSR SQWAVE ; Subroutine to generate square wave DONE: BRA DONE ; Branch to itself, Convinient for Breakpoint ;* ----------------------------------------------------------------;* Subroutine TIMERINIT: Initialize Timer for Output Compare on OC2 ;* ----------------------------------------------------------------TIMERINIT: CLR TMSK1 ; Disable All Interrupts MOVB ; ; MOVB MOVB MOVW MOVB ; ; RTS #$10,TCTL2 #$04,TIOS #$0400,TC2H #$80,TSCR #$02,TMSK2 ; Disable overflow interrupt, disable pull-up ; resistor function with normal drive capability ; and free running counter, Prescaler = sys clock/4. ; Initialize OC2 to toggle on successful compare. ; Select Channel 2 to act as output compare. ; Load TC2 Reg with initial compare value. ; Enable Timer, Timer runs during wait state, and ; while in Background Mode, also clear flags ; normally. ; Return from Subroutine MC68HC812A4 -- Rev. 3.0 210 Standard Timer Module Advance Information MOTOROLA Standard Timer Module Using the Output Compare Function to Generate a Square Wave ;* -----------------------------;* SUBROUTINE: SQWAVE ;* -----------------------------SQWAVE: ;* ------CLEARFLG: ;* ------;* To clear the C2F flag: 1) read TFLG1 when ;* C2F is set and then 2) write a logic "one" to C2F. LDAA ORAA STAA WTFLG: BRCLR LDD ADDD STD BRA RTS END TFLG1 #$04 TFLG1 TFLG1,#$04,WTFLG TC2H #$0400 TC2H CLEARFLG ; To clear OC2 Flag, first it must be read, ; then a "1" must be written to it ; Wait (Polling) for C2F Flag ; Loads value of compare from TC2 Reg. ; Add hex value of 500us High Time ; Set-up next transition time in 500 us ; Continuously add 500 us, branch to CLEARFLAG ; return from Subroutine ; End of program Advance Information MOTOROLA Standard Timer Module MC68HC812A4 -- Rev. 3.0 211 Standard Timer Module MC68HC812A4 -- Rev. 3.0 212 Standard Timer Module Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 13. Multiple Serial Interface (MSI) 13.1 Contents 13.2 13.3 13.4 13.5 13.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 SCI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 SPI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 MSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 MSI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 13.7 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .218 13.7.1 Port S Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 13.7.2 Port S Data Direction Register . . . . . . . . . . . . . . . . . . . . . .220 13.7.3 Port S Pullup and Reduced Drive Control . . . . . . . . . . . . .221 13.7.4 Port S Wired-OR Mode Control . . . . . . . . . . . . . . . . . . . . .222 13.2 Introduction The multiple serial interface (MSI) module consists of three independent serial I/O interfaces: * * Two serial communication interfaces, SCI0 and SCI1 One serial peripheral interface, SPI0 NOTE: Port S shares its pins with the multiple serial interface (MSI). See 13.7 General-Purpose I/O Ports. Advance Information MOTOROLA Multiple Serial Interface (MSI) MC68HC812A4 -- Rev. 3.0 213 Multiple Serial Interface (MSI) 13.3 SCI Features * * * * * * * Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 13-bit baud rate selection Programmable 8-bit or 9-bit data format Separately enabled transmitter and receiver Separate receiver and transmitter interrupt requests Two receiver wakeup methods: - Idle line wakeup - Address mark wakeup * Five flags with interrupt-generation capability: - Transmitter empty - Transmission complete - Receiver full - Receiver overrun - Idle receiver input * * * Receiver noise error detection Receiver framing error detection Receiver parity error detection For additional information, refer to Section 14. Serial Communications Interface Module (SCI). MC68HC812A4 -- Rev. 3.0 214 Multiple Serial Interface (MSI) Advance Information MOTOROLA Multiple Serial Interface (MSI) SPI Features 13.4 SPI Features * * * * * Full-duplex operation Master mode and slave mode Programmable slave-select output option Programmable bidirectional data pin option Interrupt-driven operation with two flags - Transmission complete - Mode fault * * * * Read data buffer Serial clock with programmable polarity and phase Reduced drive control for lower power consumption Programmable open-drain output option For additional information, refer to Section 15. Serial Peripheral Interface (SPI) 13.5 MSI Block Diagram SCI0 RxD0 TxD0 PS0 PS1 SCI1 MSI TxD1 DDRS/IOCTLR RxD1 PORT S I/O DRIVERS PS2 PS3 MOSI/MOMI SPI0 MISO/SISO SCK CS/SS PS4 PS5 PS6 PS7 Figure 13-1. Multiple Serial Interface Block Diagram Advance Information MOTOROLA Multiple Serial Interface (MSI) MC68HC812A4 -- Rev. 3.0 215 Multiple Serial Interface (MSI) 13.6 MSI Register Map Addr. Register Name SCI 0 Baud Rate Read: Register High Write: (SC0BDH) See page 249. Reset: Read: SBR7 Write: Reset: Read: LOOPS Write: Reset: Read: TIE Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: = Unimplemented R7 T7 R6 T6 R5 T5 Unaffected by reset R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 0 R8 T8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RAF 0 TDRE 0 TC 0 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PF TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 WOMS RSRC M WAKE ILT PE PT 0 0 0 0 0 1 0 0 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Bit 7 BTST 0 6 BSPL 0 5 BRLD 0 4 SBR12 0 3 SBR11 0 2 SBR10 0 1 SBR9 0 Bit 0 SBR8 0 $00C0 SCI 0 Baud Rate $00C1 Register Low (SC0BDL) See page 249. $00C2 SCI 0 Control Register 1 (SC0CR1) See page 250. $00C3 SCI 0 Control Register 2 (SC0CR2) See page 252. $00C4 SCI 0 Status Register 1 (SC0SR1) See page 254. $00C5 SCI 0 Status Register 2 (SC0SR2) See page 256. $00C6 SCI 0 Data Register High (SC0DRH) See page 257. $00C7 SCI 0 Data Register Low (SC0DRL) See page 257. Unaffected by reset Figure 13-2. MSI Register Map (Sheet 1 of 3) MC68HC812A4 -- Rev. 3.0 216 Multiple Serial Interface (MSI) Advance Information MOTOROLA Multiple Serial Interface (MSI) MSI Register Map Addr. Register Name SCI 1 Baud Rate Read: Register High Write: (SC1BDH) See page 249. Reset: Read: Bit 7 BTST 0 SBR7 Write: Reset: Read: LOOPS Write: Reset: Read: TIE Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: SPIE Write: Reset: 0 R7 T7 0 R8 1 0 0 TDRE 0 0 6 BSPL 0 SBR6 0 WOMS 0 TCIE 0 TC 5 BRLD 0 SBR5 0 RSRC 0 RIE 0 RDRF 4 SBR12 0 SBR4 0 M 0 ILIE 0 IDLE 3 SBR11 0 SBR3 0 WAKE 0 TE 0 OR 2 SBR10 0 SBR2 1 ILT 0 RE 0 NF 1 SBR9 0 SBR1 0 PE 0 RWU 0 FE Bit 0 SBR8 0 SBR0 0 PT 0 SBK 0 PF $00C8 SCI 1 Baud Rate $00C9 Register Low (SC1BDL) See page 249. SCI 1 Control Register $00CA 1 (SC1CR1) See page 250. SCI 1 Control Register $00CB 2 (SC1CR2) See page 252. SCI 1 Status Register 1 $00CC (SC1SR1) See page 254. 1 0 0 0 0 0 0 0 0 0 0 0 0 RAF SCI 1 Status Register 2 $00CD (SC1SR2) See page 256. 0 T8 0 0 0 0 0 0 0 0 0 0 0 0 $00CE SCI 1 Data Register High (SC1DRH) See page 257. Unaffected by reset R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 $00CF SCI 1 Data Register Low (SC1DRL) See page 257. Unaffected by reset SPE 0 SWOM 0 MSTR 0 CPOL 0 CPHA 0 SSOE 0 LSBF 0 SPI 0 Control Register $00D0 1 (SP0CR1) See page 273. = Unimplemented Figure 13-2. MSI Register Map (Sheet 2 of 3) Advance Information MOTOROLA Multiple Serial Interface (MSI) MC68HC812A4 -- Rev. 3.0 217 Multiple Serial Interface (MSI) Addr. Register Name Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Bit 7 0 6 0 5 0 4 0 3 PUPS 2 RDS 0 SPR2 1 0 Bit 0 SPC0 SPI 0 Control Register $00D1 2 (SP0CR2) See page 275. 0 0 0 0 0 0 0 0 1 0 0 SPR1 0 0 0 SPR0 0 0 $00D2 SPI 0 Baud Rate Register (SP0BR) See page 276. 0 SPIF 0 WCOL 0 0 0 MODF 0 0 0 0 $00D3 SPI 0 Status Register (SP0SR) See page 277. 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 $00D5 SPI 0 Data Register (SP0DR) See page 278. Write: Reset: Read: PS7 Write: Reset: Read: DDRS7 Write: Reset: 0 0 0 0 0 0 0 0 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 Unaffected by rset PS6 PS5 PS4 PS3 PS2 PS1 PS0 Unaffected by reset $00D6 Port S Data Register (PORTS) See page 219. $00D7 Port S Data Direction Register (DDRS) See page 220. = Unimplemented Figure 13-2. MSI Register Map (Sheet 3 of 3) Full register descriptions can be found in Section 14. Serial Communications Interface Module (SCI) and Section 15. Serial Peripheral Interface (SPI). 13.7 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7-PS0 are available for either general-purpose I/O or for SCI and SPI functions. MC68HC812A4 -- Rev. 3.0 218 Multiple Serial Interface (MSI) Advance Information MOTOROLA Multiple Serial Interface (MSI) General-Purpose I/O Ports 13.7.1 Port S Data Register Address: $00D6 Bit 7 Read: PS7 Write: Reset: Pin function: SS SCK MOSI Unaffected by reset MISO TXD1 RXD1 TXD0 RXD0 PS6 PS5 PS4 PS3 PS2 PS1 PS0 6 5 4 3 2 1 Bit 0 Figure 13-3. Port S Data Register (PORTS) Read: Anytime Write: Anytime PS7-PS4 -- Port S Data Bits 7-4 Port S shares PS7-PS4 with SPI0. SS is the SPI0 slave-select terminal. SCK is the SPI0 serial clock terminal. MOSI is the SPI0 master out, slave in terminal. MISO is the SPI0 master in, slave out terminal. PS3-PS0 -- Port S Data Bits 3-0 Port S shares PS3-0 with SCI1 and SCI0. TXD1 is the SCI1 transmit terminal. RXD1 is the SCI1 receive terminal. TXD0 is the SCI0 transmit terminal. RXD0 is the SCI0 receive terminal. NOTE: Reading a port S bit when its data direction bit is clear returns the level of the voltage on the pin. Reading a port S bit when its data direction bit is set returns the level of the voltage of the pin driver input. A write to a port S bit is stored in an internal latch. The latch drives the pin only when the corresponding data direction bit is set. Writes do not change the pin state when the pin is configured for SCI output. Advance Information MOTOROLA Multiple Serial Interface (MSI) MC68HC812A4 -- Rev. 3.0 219 Multiple Serial Interface (MSI) 13.7.2 Port S Data Direction Register Address: $00D7 Bit 7 Read: DDRS7 Write: Reset: 0 0 0 0 0 0 0 0 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 6 5 4 3 2 1 Bit 0 Figure 13-4. Port S Data Direction Register (DDRS) Read: Anytime Write: Anytime DDRS7-DDRS0 -- Port S Data Direction Bits These bits control the data direction of each port S pin. Setting a DDRS bit makes the pin an output; clearing a DDRS bit makes the pin an input. Reset clears the port S data direction register, configuring all port S pins as inputs. 1 = Corresponding port S pin configured as output 0 = Corresponding port S pin configured as input NOTE: When the LOOPS bit is clear, the RX pins of SCI0 and SCI1 are inputs and the TX pins are outputs regardless of their DDRS bits. When the SPI is enabled, an SPI input pin is an input regardless of its DDRS bit. When the SPI is enabled, an SPI output is an output only if its DDRS bit is set. When the DDRS bit of an SPI output is clear, the pin is available for general-purpose I/O. MC68HC812A4 -- Rev. 3.0 220 Multiple Serial Interface (MSI) Advance Information MOTOROLA Multiple Serial Interface (MSI) General-Purpose I/O Ports 13.7.3 Port S Pullup and Reduced Drive Control Address: $00D1 Bit 7 Read: Write: Reset: 0 0 0 0 1 0 0 0 0 6 0 5 0 4 0 PUPS RDS 3 2 1 0 SPC0 Bit 0 = Unimplemented Figure 13-5. SPI Control Register 2 (SP0CR2) Read: Anytime Write: Anytime PUPS -- Pullup Port S Enable Bit Setting PUPS enables internal pullup devices on all port S input pins. If a pin is programmed as output, the pullup device becomes inactive. 1 = Pullups enabled 0 = Pullups disabled RDS -- Reduced Drive Port S Bit Setting RDS lowers the drive capability of all port S output pins for lower power consumption and less noise. 1 = Reduced drive 0 = Full drive Table 13-1. Port S Pullup and Reduced Drive Enable Pullups Register Control Pins Bit Affected PUPS Reset State Reduced Drive Control Pins Bit Affected RDS Reset State SPI control register 2 (SP0CR2) PS7-PS0 Enabled PS7-PS0 Disabled SPC0 -- See Section 14. Serial Communications Interface Module (SCI). Advance Information MOTOROLA Multiple Serial Interface (MSI) MC68HC812A4 -- Rev. 3.0 221 Multiple Serial Interface (MSI) 13.7.4 Port S Wired-OR Mode Control Table 13-2. Port S Wired-OR Mode Enable Register SPI control register 1 (SP0CR1) SCI0 control register 1 (SC0CR1) SCI1 control register 1 (SC1CR1) Control Bit SWOM WOMS WOMS Pins Affected PS7-PS4 PS3, PS2 PS1, PS0 Reset State Disabled Disabled Disabled MC68HC812A4 -- Rev. 3.0 222 Multiple Serial Interface (MSI) Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 14. Serial Communications Interface Module (SCI) 14.1 Contents 14.2 14.3 14.4 14.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 14.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 14.6.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 14.6.2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 14.6.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.6.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6.3.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6.3.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 14.6.3.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 14.6.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 14.6.4.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 14.6.4.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .237 14.6.4.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 14.6.4.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 14.6.4.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .243 14.6.4.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 14.6.5 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 14.6.6 Loop Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 14.7 Register Descriptions and Reset Initialization . . . . . . . . . . . .248 14.7.1 SCI Baud Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . .249 14.7.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 14.7.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 14.7.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 14.7.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 14.7.6 SCI Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 223 Serial Communications Interface Module (SCI) 14.8 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14.8.1 TXD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14.8.2 RXD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.10.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 14.11 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 14.12 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .260 14.13 Serial Character Transmission using the SCI. . . . . . . . . . . . .260 14.13.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 14.13.2 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 14.2 Introduction The serial communications interface (SCI) allows asynchronous serial communications with peripheral devices and other MCUs. 14.3 Features Features of the SCI include: * * * * * * * Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 13-bit baud rate selection Programmable 8-bit or 9-bit data format Separately enabled transmitter and receiver Separate receiver and transmitter interrupt requests Two receiver wakeup methods: - Idle line wakeup - Address mark wakeup MC68HC812A4 -- Rev. 3.0 224 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Features * Five flags with interrupt-generation capability: - Transmitter empty - Transmission complete - Receiver full - Receiver overrun - Idle receiver input * * * Receiver noise error detection Receiver framing error detection Receiver parity error detection Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 225 Serial Communications Interface Module (SCI) 14.4 Block Diagram SCI DATA REGISTER R8 RXD RECEIVE SHIFT REGISTER RE MODULE CLOCK BAUD RATE GENERATOR RECEIVE AND WAKEUP CONTROL 16 RWU LOOPS RSRC M WAKE DATA FORMAT CONTROL ILT PE PT TE TRANSMIT CONTROL LOOPS SBK RSRC T8 TRANSMIT SHIFT REGISTER SCI DATA REGISTER TDRE TC TCIE TIE SCI INTERRUPT REQUEST SCI INTERRUPT REQUEST RIE NF FE PF RAF IDLE RDRF OR ILIE SCI INTERRUPT REQUEST SCI INTERRUPT REQUEST SBR[12:0] TXD RXD TO SCI1 TXD FROM SCI1 WOMS PIN CONTROL LOGIC PORT S DATA DIRECTION REGISTER PORT S DATA REISTER 3210 RXD0 TXD0 RXD1 TXD1 Figure 14-1. SCI Block Diagram MC68HC812A4 -- Rev. 3.0 226 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Register Map 14.5 Register Map NOTE: The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Bit 7 BTST 0 SBR7 Write: Reset: Read: LOOPS Write: Reset: Read: TIE Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: = Unimplemented Unaffected by reset 0 R8 T8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RAF 0 TDRE 0 TC 0 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PF TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 WOMS RSRC M WAKE ILT PE PT 0 0 0 0 0 1 0 0 6 BSPL 0 SBR6 5 BRLD 0 SBR5 4 SBR12 0 SBR4 3 SBR11 0 SBR3 2 SBR10 0 SBR2 1 SBR9 0 SBR1 Bit 0 SBR8 0 SBR0 Addr. Register Name SCI 0 Baud Rate Read: Register High Write: (SC0BDH) See page 249. Reset: Read: $00C0 SCI 0 Baud Rate $00C1 Register Low (SC0BDL) See page 249. $00C2 SCI 0 Control Register 1 (SC0CR1) See page 250. $00C3 SCI 0 Control Register 2 (SC0CR2) See page 252. $00C4 SCI 0 Status Register 1 (SC0SR1) See page 254. $00C5 SCI 0 Status Register 2 (SC0SR2) See page 256. $00C6 SCI 0 Data Register High (SC0DRH) See page 257. Figure 14-2. SCI Register Map (Sheet 1 of 2) Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 227 Serial Communications Interface Module (SCI) Addr. Register Name SCI 0 Data Register Low (SC0DRL) See page 257. Read: Write: Reset: Bit 7 R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 $00C7 Unaffected by reset BTST 0 SBR7 BSPL 0 SBR6 0 WOMS 0 TCIE 0 TC BRLD 0 SBR5 0 RSRC 0 RIE 0 RDRF SBR12 0 SBR4 0 M 0 ILIE 0 IDLE SBR11 0 SBR3 0 WAKE 0 TE 0 OR SBR10 0 SBR2 1 ILT 0 RE 0 NF SBR9 0 SBR1 0 PE 0 RWU 0 FE SBR8 0 SBR0 0 PT 0 SBK 0 PF $00C8 SCI 1 Baud Rate Read: Register High Write: (SC1BDH) See page 249. Reset: Read: Write: Reset: Read: SCI 1 Baud Rate $00C9 Register Low (SC1BDL) See page 249. 0 LOOPS SCI 1 Control Register $00CA 1 (SC1CR1) See page 250. Write: Reset: Read: TIE Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: = Unimplemented R7 T7 R6 T6 R5 T5 Unaffected by reset R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 0 R8 T8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RAF 0 TDRE 0 SCI 1 Control Register $00CB 2 (SC1CR2) See page 252. SCI 1 Status Register 1 $00CC (SC1SR1) See page 254. SCI 1 Status Register 2 $00CD (SC1SR2) See page 256. $00CE SCI 1 Data Register High (SC1DRH) See page 257. $00CF SCI 1 Data Register Low (SC1DRL) See page 257. Unaffected by reset Figure 14-2. SCI Register Map (Sheet 2 of 2) MC68HC812A4 -- Rev. 3.0 228 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description 14.6 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. 14.6.1 Data Format The SCI uses the standard NRZ mark/space data format illustrated in Figure 14-3. 8-BIT DATA FORMAT BIT M IN SCCR1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY OR DATA BIT BIT 7 STOP BIT PARITY OR DATA BIT BIT 7 BIT 8 NEXT START BIT 9-BIT DATA FORMAT BIT M IN SCCR1 SET START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT NEXT START BIT Figure 14-3. SCI Data Formats Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for 9-bit data characters. A frame with nine data bits has a total of 11 bits. Table 14-1. Example 8-Bit Data Formats Start Bit 1 1 1 1 Data Bits 8 7 7 7 Address Bit 0 0 0 1(1) 1 Parity Bit 0 Stop Bit 1 2 1 1 1. The address bit identifies the frame as an address character. See 14.6.4.6 Receiver Wakeup. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 229 Serial Communications Interface Module (SCI) Setting the M bit configures the SCI for 9-bit data characters. The ninth data bit is the T8 bit in SCI data register high (SCDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 14-2. Example 9-Bit Data Formats Start Bit 1 1 1 1 Data Bits 9 8 8 8 Address Bit 0 0 0 1(1) 1 Parity Bit 0 Stop Bit 1 2 1 1 1. The address bit identifies the frame as an address character. See 14.6.4.6 Receiver Wakeup. 14.6.2 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12-SBR0 bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCBDH and SCBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to two sources of error: * * Integer division of the module clock may not give the exact target frequency. Synchonization with the bus clock can cause phase shift. Table 14-3 lists some examples of achieving target baud rates with a module clock frequency of 10.2 MHz. MC68HC812A4 -- Rev. 3.0 230 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description Table 14-3. Baud Rates (Module Clock = 10.2 MHz) Baud Rate Divisor(1) 17 33 66 133 266 531 1062 2125 4250 5795 Receiver Clock Rate (Hz)(2) 600,000.0 309,090.9 154,545.5 76,691.7 38,345.9 19,209.0 9604.5 4800.0 2400.0 1760.1 Transmitter Clock Rate (Hz)(3) 37,500.0 19,318.2 9659.1 4793.2 2396.6 1200.6 600.3 300.0 150.0 110.0 Target Baud Rate 38,400 19,200 9600 4800 2400 1200 600 300 150 110 Error (%) 2.3 0.62 0.62 0.14 0.14 0.11 0.05 0.00 0.00 0.00 1. The baud rate divisor is the value written to the SBR12-SBR0 bits. 2. The receiver clock frequency is the MCLK frequency divided by the baud rate divisor. 3. The transmitter clock frequency is the receiver clock frequency divided by 16. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 231 Serial Communications Interface Module (SCI) 14.6.3 Transmitter A block diagram of the SCI transmitter is shown in Figure 14-4. INTERNAL BUS MODULE CLOCK BAUD DIVIDER 16 SCI DATA REGISTERS 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 M H START L SBR12-SBR0 STOP TXD MSB LOAD FROM SCIDR PREAMBLE (ALL 1s) T8 SHIFT ENABLE LOOP CONTROL BREAK (ALL 0s) TO RECEIVER PE PT PARITY GENERATION LOOPS RSRC TRANSMITTER CONTROL SCI INTERRUPT REQUEST TDRE TIE TC TCIE TE SBK SCI INTERRUPT REQUEST Figure 14-4. SCI Transmitter Block Diagram MC68HC812A4 -- Rev. 3.0 232 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description 14.6.3.1 Character Length The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCCR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCDRH) is the ninth bit (bit 8). 14.6.3.2 Character Transmission During an SCI transmission, the transmit shift register shifts a frame out to the TXD pin. The SCI data registers (SCDRH and SCDRL) are the write-only buffers between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the transmitter by writing a logic 1 to the transmitter enable bit, TE, in SCI control register 2 (SCCR2). 2. Clear the transmit data register empty flag, TDRE, by first reading SCI status register 1 (SCSR1) and then writing to SCI data register low (SCDRL). In 9-data-bit format, write the ninth bit to the T8 bit in SCI data register high (SCDRH). 3. Repeat step 2 for each subsequent transmission. Writing the TE bit from 0 to 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCSR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCCR2) is also set, the TDRE flag generates an SCI interrupt request. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 233 Serial Communications Interface Module (SCI) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCCR2), the transmitter and receiver relinquish control of the port I/O pins. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. Then the TXD pin reverts to being a general-purpose I/O pin even if there is data pending in the SCI data register. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCDRH/L. When the SCI relinquishes the TXD pin, the PORTS and DDRS registers control the TXD pin. To force TXD high when turning off the transmitter, set bit 1 of the port S register (PORTS) and bit 1 of the port S data direction register (DDRS). The TXD pin goes high as soon as the SCI relinquishes it. 14.6.3.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCCR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCCR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a MC68HC812A4 -- Rev. 3.0 234 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: * * * * Sets the framing error flag, FE Sets the receive data register full flag, RDRF Clears the SCI data registers, SCDRH/L May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see 14.7.4 SCI Status Register 1) 14.6.3.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCCR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out to the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character when the TDRE flag becomes set and immediately before writing the next byte to the SCI data register. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 235 Serial Communications Interface Module (SCI) 14.6.4 Receiver A block diagram of the SCI receiver is shown in Figure 14-5. INTERNAL BUS SBR12-SBR0 SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0 RXD FROM TXD PIN OR TRANSMITTER LOOP CONTROL RE LOOPS RSRC RAF DATA RECOVERY H ALL 1s MSB FE M WAKE ILT PE PT WAKEUP LOGIC NF PE RWU PARITY CHECKING IDLE ILIE RDRF R8 SCI INTERRUPT REQUEST SCI INTERRUPT REQUEST RIE OR Figure 14-5. SCI Receiver Block Diagram MC68HC812A4 -- Rev. 3.0 236 Serial Communications Interface Module (SCI) Advance Information MOTOROLA START L STOP MODULE CLOCK BAUD DIVIDER Serial Communications Interface Module (SCI) Functional Description 14.6.4.1 Character Length The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCCR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCDRH) is the ninth bit (bit 8). 14.6.4.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCSR1) becomes set, indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCCR2) is also set, the RDRF flag generates an interrupt request. 14.6.4.3 Data Sampling The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 14-6) is resynchronized: * * After every start bit After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 237 Serial Communications Interface Module (SCI) START BIT RXD SAMPLES 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 LSB START BIT QUALIFICATION START BIT VERIFICATION DATA SAMPLING RT CLOCK RT4 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT4 Figure 14-6. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 14-4 summarizes the results of the start bit verification samples. Table 14-4. Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC68HC812A4 -- Rev. 3.0 238 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-5 summarizes the results of the data bit samples. Table 14-5. Data Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0 NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-6 summarizes the results of the stop bit samples. Table 14-6. Stop Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 239 Serial Communications Interface Module (SCI) In Figure 14-7 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. In Figure 14-8 noise is perceived as the beginning of a start bit although the verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. START BIT RXD SAMPLES 1 1 1 0 1 1 1 0 0 0 0 0 0 0 LSB RT CLOCK RT3 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 LSB RT6 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT3 RT7 Figure 14-7. Start Bit Search Example 1 PERCEIVED START BIT ACTUAL START BIT RXD SAMPLES 1 1 1 1 1 0 1 0 0 0 0 0 RT CLOCK RT7 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT8 RT9 RT1 RT2 RT3 RT4 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT5 Figure 14-8. Start Bit Search Example 2 MC68HC812A4 -- Rev. 3.0 240 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description In Figure 14-9 a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Figure 14-10 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. PERCEIVED START BIT ACTUAL START BIT RXD SAMPLES 1 1 1 0 0 1 0 0 0 0 LSB RT CLOCK RT9 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 LSB RT2 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT9 RT3 Figure 14-9. Start Bit Search Example 3 PERCEIVED AND ACTUAL START BIT RXD SAMPLES 1 1 1 1 1 1 1 1 1 0 1 0 RT CLOCK RT3 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT1 Figure 14-10. Start Bit Search Example 4 Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 241 Serial Communications Interface Module (SCI) Figure 14-11 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. In Figure 14-12 a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. RXD SAMPLES 1 1 1 1 1 1 1 1 1 0 0 1 START BIT NO START BIT FOUND 1 0 0 0 0 0 0 0 0 LSB RT CLOCK RT3 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT4 RT5 RT6 RT7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 LSB RT2 RT CLOCK COUNT RESET RT CLOCK RT1 RT3 Figure 14-11. Start Bit Search Example 5 START BIT RXD SAMPLES 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 RT CLOCK RT3 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT1 Figure 14-12. Start Bit Search Example 6 MC68HC812A4 -- Rev. 3.0 242 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description 14.6.4.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCSR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. 14.6.4.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming frame, it resynchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 14-13 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 14-13. Slow Data Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 243 Serial Communications Interface Module (SCI) For an 8-bit data character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 14-13, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: 154 - 147 ------------------------- x 100 = 4.54% 154 For a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 14-13, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: 170 - 163 ------------------------- x 100 = 4.12% 170 Fast Data Tolerance Figure 14-14 shows how much a fast received frame can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. STOP IDLE OR NEXT FRAME RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 14-14. Fast Data MC68HC812A4 -- Rev. 3.0 244 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Functional Description For an 8-bit data character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 14-14, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: 154 - 160 ------------------------- x 100 = 3.90% 154 For a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 14-14, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 170 - 176 ------------------------- x 100 = 3.53% 170 14.6.4.6 Receiver Wakeup So that the SCI can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCCR2) puts the receiver into a standby state during which receiver interrupts are disabled. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 245 Serial Communications Interface Module (SCI) The WAKE bit in SCI control register 1 (SCCR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup: * Idle input line wakeup (WAKE = 0) -- In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle flag, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCCR1). * Address mark wakeup (WAKE = 1) -- In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver's RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE: With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately. Advance Information Serial Communications Interface Module (SCI) MOTOROLA MC68HC812A4 -- Rev. 3.0 246 Serial Communications Interface Module (SCI) Functional Description 14.6.5 Single-Wire Operation Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI and is available as a general-purpose I/O pin. The SCI uses the TXD pin for both receiving and transmitting. Setting the data direction bit for the TXD pin configures TXD as the output for transmitted data. Clearing the data direction bit configures TXD as the input for received data. TRANSMITTER DDRS BIT = 1 RECEIVER TXD WOMS RXD GENERALPURPOSE I/O TRANSMITTER DDRS BIT = 0 RECEIVER NC TXD RXD GENERALPURPOSE I/O Figure 14-15. Single-Wire Operation (LOOPS = 1 and RSRC = 1) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCCR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the receiver input to the output of the TXD pin driver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). The wired-OR mode select bit, WOMS, configures the TXD pin for full CMOS drive or for open-drain drive. WOMS controls the TXD pin in both normal operation and in single-wire operation. When WOMS is set, the data direction bit for the TXD pin does not have to be cleared for TXD to receive data. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 247 Serial Communications Interface Module (SCI) 14.6.6 Loop Operation In loop operation, the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI and is available as a general-purpose I/O pin. Setting the data direction bit for the TXD pin connects the transmitter output to the TXD pin. Clearing the data direction bit disconnects the transmitter output from the TXD pin. TRANSMITTER DDRS BIT = 1 RECEIVER TXD WOMS RXD GENERALPURPOSE I/O TRANSMITTER DDRS BIT = 0 RECEIVER H TXD WOMS RXD GENERALPURPOSE I/O Figure 14-16. Loop Operation (LOOP = 1 and RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCCR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). The wired-OR mode select bit, WOMS, configures the TXD pin for full CMOS drive or for open-drain drive. WOMS controls the TXD pin in both normal operation and in loop operation. 14.7 Register Descriptions and Reset Initialization This section provides register descriptions and reset initialization. MC68HC812A4 -- Rev. 3.0 248 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Register Descriptions and Reset Initialization 14.7.1 SCI Baud Rate Registers SCI0: $00C0 SCI1: $00C8 Bit 7 Read: Write: Reset: BTST 0 6 BSPL 0 5 BRLD 0 4 SBR12 0 3 SBR11 0 2 SBR10 0 1 SBR9 0 Bit 0 SBR8 0 Figure 14-17. SCI Baud Rate Register High (SC0BDH or SC1BDH) SCI0: $00C1 SCI1: $00C9 Bit 7 Read: Write: Reset: SBR7 0 6 SBR6 0 5 SBR5 0 4 SBR4 0 3 SBR3 0 2 SBR2 1 1 SBR1 0 Bit 0 SBR0 0 Figure 14-18. SCI Baud Rate Register Low (SC0BDL or SC1BDL) Read: Anytime Write: SBR[12:0] anytime; BTST, BSPL, and BRLD only in special modes BTST -- Reserved for test function BSPL -- Reserved for test function BRLD -- Reserved for test function SBR[12:0] -- SCI Baud Rate Bits The value written to SBR[12:0] determines the baud rate of the SCI. The new value takes effect when the low order byte is written. The formula for calculating baud rate is: MCLK SCI baud rate = -------------------16 x BR BR = value written to SBR[12:0], a value from 1 to 8191 NOTE: The baud rate generator is disabled until the TE bit or the RE bit is set for the first time after reset. The baud rate generator is disabled when BR = 0. MC68HC812A4 -- Rev. 3.0 Serial Communications Interface Module (SCI) 249 Advance Information MOTOROLA Serial Communications Interface Module (SCI) 14.7.2 SCI Control Register 1 SCI0: $00C2 SCI1: $00CA Bit 7 Read: Write: Reset: LOOPS 0 6 WOMS 0 5 RSRC 0 4 M 0 3 WAKE 0 2 ILT 0 1 PE 0 Bit 0 PT 0 Figure 14-19. SCI Control Register 1 (SC0CR1 or SC1CR1) Read: Anytime Write: Anytime LOOPS -- Loop Select Bit LOOPS enables loop operation. In loop operation the RXD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 1 = Loop operation enabled 0 = Normal operation enabled The receiver input is determined by the RSRC bit. The transmitter output is controlled by the associated DDRS bit. If the data direction bit for the TXD pin is set and LOOPS = 1, the transmitter output appears on the TXD pin. If the DDRS bit is clear and LOOPS = 1, the TXD pin is idle (high) if RSRC = 0 and high-impedance if RSRC = 1. See Table 14-7. WOMS -- Wired-OR Mode Select Bit WOMS configures the TXD and RXD pins for open-drain operation. WOMS allows TXD pins to be tied together in a multiple-transmitter system. Then the TXD pins of non-active transmitters follow the logic level of an active 1. WOMS also affects the TXD and RXD pins when they are general-purpose outputs. External pullup resistors are necessary on open-drain outputs. 1 = TXD and RXD pins, open-drain when outputs 0 = TXD and RXD pins, full CMOS drive capability MC68HC812A4 -- Rev. 3.0 250 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Register Descriptions and Reset Initialization RSRC -- Receiver Source Bit When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver. 1 = Receiver input connected to TXD pin 0 = Receiver input internally connected to transmitter output Table 14-7. Loop Mode Functions LOOPS 0 1 1 1 1 1 1 RSRC X 0 0 0 1 1 1 DDRSx(1) X 0 1 1 0 1 1 WOMS X X 0 1 x 0 1 Normal operation Function of TXD Pin Loop mode; transmitter output connected to receiver input TXD pin disconnected Loop mode; transmitter output connected to receiver input TXD is CMOS output Loop mode; transmitter output connected to receiver input TXD is open-drain output Single-wire mode; transmitter output disconnected TXD is high-impedance receiver input Single-wire mode; TXD pin connected to receiver input Single wire mode; TXD pin connected to receiver input TXD is open-drain for receiving and transmitting 1. DDRSx means the data direction bit of the TXD pin. M -- Mode Bit M determines whether data characters are eight or nine bits long. 1 = One start bit, nine data bits, one stop bit 0 = One start bit, eight data bits, one stop bit WAKE -- Wakeup Bit WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD pin. 1 = Address mark wakeup 0 = Idle line wakeup Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 251 Serial Communications Interface Module (SCI) ILT -- Idle Line Type Bit ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 1 = Idle character bit count begins after stop bit. 0 = Idle character bit count begins after start bit. PE -- Parity Enable Bit PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 1 = Parity function enabled 0 = Parity function disabled PT -- Parity Type Bit PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 1 = Odd parity 0 = Even parity 14.7.3 SCI Control Register 2 SCI0: $00C3 SCI1: $00CB Bit 7 Read: Write: Reset: TIE 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0 Figure 14-20. SCI Control Register 2 (SC0CR2 or SC1CR2) Read: Anytime Write: Anytime MC68HC812A4 -- Rev. 3.0 252 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Register Descriptions and Reset Initialization TIE -- Transmitter Interrupt Enable Bit TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 1 = TDRE interrupt requests enabled 0 = TDRE interrupt requests disabled TCIE -- Transmission Complete Interrupt Enable Bit TCIE enables the transmission complete flag, TC, to generate interrupt requests. 1 = TC interrupt requests enabled 0 = TC interrupt requests disabled RIE -- Receiver Interrupt Enable Bit RIE enables the receive data register full flag, RDRF, and the overrun flag, OR, to generate interrupt requests. 1 = RDRF and OR interrupt requests enabled 0 = RDRF and OR interrupt requests disabled ILIE -- Idle Line Interrupt Enable Bit ILIE enables the idle line flag, IDLE, to generate interrupt requests. 1 = IDLE interrupt requests enabled 0 = IDLE interrupt requests disabled TE -- Transmitter Enable Bit TE enables the SCI transmitter and configures the TXD pin as the SCI transmitter output. The TE bit can be used to queue an idle preamble. 1 = Transmitter enabled 0 = Transmitter disabled RE -- Receiver Enable Bit RE enables the SCI receiver. 1 = Receiver enabled 0 = Receiver disabled RWU -- Receiver Wakeup Bit 1 = Standby state 0 = Normal operation Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 253 Serial Communications Interface Module (SCI) RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. SBK -- Send Break Bit Toggling SBK sends one break character (10 or 11 logic 0s). As long as SBK is set, the transmitter sends logic 0s. 1 = Transmit break characters 0 = No break characters 14.7.4 SCI Status Register 1 SCI0: $00C4 SCI1: $00CC Bit 7 Read: Write: Reset: 1 1 0 0 0 0 0 0 TDRE 6 TC 5 RDRF 4 IDLE 3 OR 2 NF 1 FE Bit 0 PF = Unimplemented Figure 14-21. SCI Status Register 1 (SC0SR1 or SC1SR1) Read: Anytime Write: Has no meaning or effect TDRE -- Transmit Data Register Empty Flag TDRE is set when the transmit shift register receives a byte from the SCI data register. Clear TDRE by reading SCI status register 1 with TDRE set and then writing to the low byte of the SCI data register. 1 = Transmit data register empty 0 = Transmit date register not empty TC -- Transmission Complete Flag TC is set when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 with TC set MC68HC812A4 -- Rev. 3.0 254 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Register Descriptions and Reset Initialization and then writing to the low byte of the SCI data register. TC clears automatically when a break, preamble, or data is queued and ready to be sent. 1 = Transmission complete 0 = Transmission in progress RDRF -- Receive Data Register Full Flag RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 with RDRF set and then reading the low byte of the SCI data register. 1 = Receive data register full 0 = Data not available in SCI data register IDLE -- Idle Line Flag IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Clear IDLE by reading SCI status register 1 with IDLE set and then writing to the low byte of the SCI data register. Once IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. 1 = Receiver input has become idle 0 = Receiver input is either active now or has never become active since the IDLE flag was last cleared NOTE: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. OR -- Overrun Flag OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 with OR set and then reading the low byte of the SCI data register. 1 = Overrun 0 = No overrun Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 255 Serial Communications Interface Module (SCI) NF -- Noise Flag NF is set when the SCI detects noise on the receiver input. NF is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1 and then reading the low byte of the SCI data register. 1 = Noise 0 = No noise FE -- Framing Error Flag FE is set when a logic 0 is accepted as the stop bit. FE is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 with FE set and then reading the low byte of the SCI data register. 1 = Framing error 0 = No framing error PF -- Parity Error Flag PF is set when the parity enable bit, PE, is set and the parity of the received data does not match its parity bit. Clear PF by reading SCI status register 1 and then reading the low byte of the SCI data register. 1 = Parity error 0 = No parity error 14.7.5 SCI Status Register 2 SCI0: $00C5 SCI1: $00CD Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 RAF = Unimplemented Figure 14-22. SCI Status Register 2 (SC0SR2 or SC1SR2) Read: Anytime Write: Has no meaning or effect MC68HC812A4 -- Rev. 3.0 256 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Register Descriptions and Reset Initialization RAF -- Receiver Active Flag RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects false start bits (usually from noise or baud rate mismatch) or when the receiver detects an idle character. 1 = Reception in progress 0 = No reception in progress 14.7.6 SCI Data Registers SCI0: $00C6 SCI1: $00CE Bit 7 Read: Write: Reset: = Unimplemented Unaffected by reset R8 T8 6 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Figure 14-23. SCI Data Register High (SC0DRH or SC1DRH) SCI0: $00C7 SCI1: $00CF Bit 7 Read: Write: Reset: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 Unaffected by reset Figure 14-24. SCI Data Register Low (SC0DRL or SC1DRL) Read: Anytime; reading accesses receive data register Write: Anytime; writing accesses transmit data register; writing to R8 has no effect Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 257 Serial Communications Interface Module (SCI) R8 -- Received Bit 8 R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). T8 -- Transmitted Bit 8 T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). R7-R0 -- Received Bits 7-0 T7-T0 -- Transmitted Bits 7-0 NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten. The same value is transmitted until T8 is rewritten. In 8-bit data format, only SCI data register low (SCDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCDRH). 14.8 External Pin Descriptions This section provides a description of TXD and RXD, the SCI's two external pins. 14.8.1 TXD Pin TXD is the SCI transmitter pin. TXD is available for general-purpose I/O when it is not configured for transmitter operation. 14.8.2 RXD Pin RXD is the SCI receiver pin. RXD is available for general-purpose I/O when it is not configured for receiver operation. MC68HC812A4 -- Rev. 3.0 258 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Modes of Operation 14.9 Modes of Operation The SCI functions the same in normal, special, and emulation modes. 14.10 Low-Power Options This section provides a description of the three low-power modes: * * * Run mode Wait mode Stop mode 14.10.1 Run Mode Clearing the transmitter enable or receiver enable bits (TE or RE) in SCI control register 2 (SCCR2) reduces power consumption in run mode. SCI registers are still accessible when TE or RE is cleared, but clocks to the core of the SCI are disabled. 14.10.2 Wait Mode The SCI remains active in wait mode. Any enabled interrupt request from the SCI can bring the MCU out of wait mode. If SCI functions are not required during wait mode, reduce power consumption by disabling the SCI before executing the WAIT instruction. 14.10.3 Stop Mode For reduced power consumption, the SCI is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI operation resumes after an external interrupt. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 259 Serial Communications Interface Module (SCI) 14.11 Interrupt Sources Table 14-8. SCI Interrupt Sources Interrupt Source Transmit data register empty Transmission complete Receive data register full Receiver overrun Receiver idle Flag Local Enable TIE TCIE RIE OR IDLE ILIE I bit CCR Mask I bit I bit I bit $FFD6, $FFD7 $FFD4, $FFD5 Vector Address SCI0 TDRE TC RDRF SCI1 14.12 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7-PS0 are available for either general-purpose I/O or for SCI and SPI functions. See Section 13. Multiple Serial Interface (MSI). 14.13 Serial Character Transmission using the SCI Code is intended to use SCI1 to serially transmit characters using polling to the LCD display on the UDLP1 board: when the transmission data register is empty a flag will get set, which is telling us that SC1DR is ready so we can write another byte. The transmission is performed at a baud rate of 9600. Since the SCI1 is only being used for transmit data, the data register will not be used bidirectionally for received data. 14.13.1 Equipment For this exercise, use the M68HC812A4EVB emulation board. MC68HC812A4 -- Rev. 3.0 260 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Serial Communications Interface Module (SCI) Serial Character Transmission using the SCI 14.13.2 Code Listing NOTE: A comment line is deliminted by a semi-colon. If there is no code before comment, an ";" must be placed in the first column to avoid assembly errors. ; Equates for registers INCLUDE 'EQUATES.ASM' ; User Variables ; Bit Equates ; ---------------------------------------------------------------------; MAIN PROGRAM ; ---------------------------------------------------------------------ORG $7000 ; 16K On-Board RAM, User code data area, ; ; start main program at $4000 MAIN: BSR INIT ; Subroutine to Initialize SCI0 registers BSR TRANS ; Subroutine to start transmission DONE: BRA DONE ; Always branch to DONE, convenient for breakpoint ; ---------------------------------------------------------------------; SUBROUTINE INIT: ; ---------------------------------------------------------------------INIT: TPA ; Transfer CCR to A accumulator ORAA #$10 ; ORed A with #$10 to Set I bit TAP ; Transfer A to CCR MOVB MOVB ; MOVB LDAA STD LDX RTS #$08,SC1CR2 SC1SR1 SC1DRH #DATA #$34,SC1BDL #$00,SC1CR1 ; Set BAUD =9600, in SCI1 Baud Rate Reg. ; Initialize for 8-bit Data format, ; Loop Mode and parity disabled,(SC1CR1) ; Set for No Ints, and Transmitter enabled(SC1CR2) ; 1st step to clear TDRE flag: Read SC1SR1 ; 2nd step to clear TDRE flag: Write SC1DR register ; Use X as a pointer to DATA. ; Return from subroutine ; ---------------------------------------------------------------------; TRANSMIT SUBROUTINE ; ---------------------------------------------------------------------TRANS: BRCLR SC1SR1,#$80, TRANS ; Wait for TDRE flag MOVB 1,X+,SC1DRL ; Transmit character, increment X pointer CPX #EOT ; Detect if last character has been transmitted BNE TRANS ; If last char. not equal to "eot", Branch to TRANS RTS ; else Transmission complete, Return from Subroutine ; ---------------------------------------------------------------------; TABLE : DATA TO BE TRANSMITTED ; ---------------------------------------------------------------------DATA: DC.B 'Motorola HC12 Banner - June, 1999' DC.B $0D,$0A ; Return (cr) ,Line Feed (LF) DC.B 'Scottsdale, Arizona' DC.B $0D,$0A ; Return (cr) ,Line Feed (LF) EOT: DC.B $04 ; Byte used to test end of data = EOT END ; End of program Advance Information MOTOROLA Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 261 Serial Communications Interface Module (SCI) MC68HC812A4 -- Rev. 3.0 262 Serial Communications Interface Module (SCI) Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 15. Serial Peripheral Interface (SPI) 15.1 Contents 15.2 15.3 15.4 15.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 15.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 15.6.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 15.6.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 15.6.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 15.6.4 Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . .268 15.6.5 SS Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 15.6.6 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 15.7 SPI Register Descriptions and Reset Initialization . . . . . . . . .273 15.7.1 SPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 15.7.2 SPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 15.7.3 SPI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . .276 15.7.4 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 15.7.5 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 15.8 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 15.8.1 MISO (Master In, Slave Out) . . . . . . . . . . . . . . . . . . . . . . .279 15.8.2 MOSI (Master Out, Slave In) . . . . . . . . . . . . . . . . . . . . . . .279 15.8.3 SCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 15.8.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 15.9.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 15.10 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 15.11 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 263 Serial Peripheral Interface (SPI) 15.12 Synchronous Character Transmission using the SPI . . . . . . .282 15.12.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 15.12.2 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 15.2 Introduction The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communications with peripheral devices. 15.3 Features Features of the SPI include: * * * * * Full-duplex operation Master mode and slave mode Programmable slave-select output option Programmable bidirectional data pin option Two flags with interrupt-generation capability: - Transmission complete - Mode fault * * * * * Write collision detection Read data buffer Serial clock with programmable polarity and phase Reduced drive control for lower power consumption Programmable open-drain output option MC68HC812A4 -- Rev. 3.0 264 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) Block Diagram 15.4 Block Diagram MSTR BAUD RATE SELECT CPHA CPOL P-CLOCK CLOCK DIVIDER PUPS RDS SWOM SSOE SPE SPI CONTROL MSTR SPC0 PIN CONTROL LOGIC MODF WCOL SPIF SPIE INTERRUPT REQUEST PORT S DATA DIRECTION REGISTER PORT S DATA REG. 7654 SHIFT CONTROL LOGIC SPI DATA REGISTER (READ) SPI DATA REGISTER (WRITE) CLOCK LOGIC SHIFT REGISTER SPR2 SPR1 SPR0 LSBF MISO OR SISO MOSI OR MOMI SCK SS Figure 15-1. SPI Block Diagram Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 265 Serial Peripheral Interface (SPI) 15.5 Register Map NOTE: The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Bit 7 SPIE 0 0 0 0 0 SPIF 0 Bit 7 6 SPE 0 0 0 0 0 WCOL 0 6 5 SWOM 0 0 0 0 0 0 0 5 4 MSTR 0 0 0 0 0 MODF 0 4 3 CPOL 0 PUPS 1 0 0 0 0 3 2 CPHA 1 RDS 0 SPR2 0 0 0 2 1 SSOE 0 0 0 SPR1 0 0 0 1 Bit 0 LSBF 0 SPC0 0 SPR0 0 0 0 0 Addr. $00D0 Register Name SPI 0 Control Read: Register 1 (SP0CR1) Write: See page 273. Reset: SPI 0 Control Read: Register 2 (SP0CR2) Write: See page 275. Reset: $00D1 SPI Baud Rate Register Read: $00D2 (SP0BR) Write: See page 276. Reset: $00D3 SPI Status Register Read: (SP0SR) Write: See page 277. Reset: SPI Data Register Read: (SP0DR) Write: See page 278. Reset: Port S Data Register Read: (PORTS) Write: See page 219. Reset: Port S Data Direction Read: Register (DDRS) Write: See page 220. Reset: $00D5 Unaffected by reset PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 $00D6 Unaffected by reset DDRS7 0 DDRS6 0 DDRS5 0 DDRS4 0 DDRS3 0 DDRS2 0 DDRS1 0 DDRS0 0 $00D7 = Unimplemented Figure 15-2. SPI Register Map 15.6 Functional Description The SPI allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. In master mode, the SPI generates the synchronizing clock and initiates transmissions. In MC68HC812A4 -- Rev. 3.0 266 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) Functional Description slave mode, the SPI depends on a master peripheral to start and synchronize transmissions. 15.6.1 Master Mode The SPI operates in master mode when the master mode bit, MSTR, is set. NOTE: Configure SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. Only a master SPI module can initiate transmissions. Begin the transmission from a master SPI module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the master out, slave in pin (MOSI) under the control of the serial clock. See Figure 15-3. As the byte shifts out on the MOSI pin, a byte shifts in from the slave on the master in, slave out pin (MISO) pin. On the eighth serial clock cycle, the transmission ends and sets the SPI flag, SPIF. At the same time that SPIF becomes set, the byte from the slave transfers from the shift register to the SPI data register. The byte remains in a read buffer until replaced by the next byte from the slave. MASTER MCU SLAVE MCU SHIFT REGISTER MISO MOSI SCK MISO MOSI SCK SS SHIFT REGISTER CLOCK DIVIDER SS VDD Figure 15-3. Full-Duplex Master/Slave Connections Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 267 Serial Peripheral Interface (SPI) 15.6.2 Slave Mode The SPI operates in slave mode when MSTR is clear. In slave mode, the SCK pin is the input for the serial clock from the master. NOTE: Before a transmission occurs, the SS pin of the slave SPI must be at logic 0. The slave SS pin must remain low until the transmission is complete. A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. On the eighth serial clock cycle, the transmission ends and sets the SPI flag, SPIF. At the same time that SPIF becomes set, the byte from the master transfers to the SPI data register. The byte remains in a read buffer until replaced by the next byte from the master. 15.6.3 Baud Rate Generation A clock divider in the SPI produces eight divided P-clock signals. The P-clock divisors are 2, 4, 8, 16, 32, 64, 128, and 256. The SPR[2:1:0] bits select one of the divided P-clock signals to control the rate of the shift register. Through the SCK pin, the selected clock signal also controls the rate of the shift register of the slave SPI or other slave peripheral. The clock divider is active only in master mode and only when a transmission is taking place. Otherwise, the divider is disabled to save power. 15.6.4 Clock Phase and Polarity The clock phase and clock polarity bits, CPHA and CPOL, can select any of four combinations of serial clock phase and polarity. The CPHA bit determines whether a falling SS edge or the first SCK edge begins the transmission. The CPOL bit determines whether SCK is active-high or active-low. MC68HC812A4 -- Rev. 3.0 268 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) Functional Description NOTE: To transmit between SPI modules, both modules must have identical CPHA and CPOL values. When CPHA = 0, a falling SS edge signals the slave to begin transmission. The capture strobe for the first bit occurs on the first serial clock edge. Therefore, the slave must begin driving its data before the first serial clock edge. After transmission of all eight bits, the slave SS pin must toggle from low to high to low again to begin another transmission. This format may be preferable in systems having more than one slave driving the master MISO line. BEGIN TRANSFER SCK CYCLES SCK CPOL = 0 SCK CPOL = 1 MOSI FROM MASTER MISO FROM SLAVE SS TO SLAVE CAPTURE STROBE MSB FIRST (LSBF = 0) LSB FIRST (LSBF = 1) tL 1 2 3 4 5 6 END TRANSFER 7 8 tT tI MSB LSB BIT 6 BIT 1 BIT 5 BIT 2 BIT 4 BIT 3 BIT 3 BIT 4 BIT 2 BIT 5 BIT 1 BIT 6 LSB MSB MINIMUM tL, tT, and tI = 1/2 SCK CYCLE Figure 15-4. Transmission Format 0 (CPHA = 0) MISO/MOSI MASTER SS SLAVE SS CPHA = 0 BYTE 1 BYTE 2 BYTE 3 Figure 15-5. Slave SS Toggling When CPHA = 0 Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 269 Serial Peripheral Interface (SPI) When CPHA = 1, the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can remain low between transmissions. This format may be preferable in systems having only one slave driving the master MISO line. NOTE: The slave SCK pin must be in the proper idle state before the slave is enabled. tL SCK CYCLES SCK CPOL = 0 SCK CPOL = 1 MOSI FROM MASTER MISO FROM SLAVE SS TO SLAVE CAPTURE STROBE MSB FIRST (LSBF = 0) LSB FIRST (LSBF = 1) BEGIN TRANSFER 1 2 3 4 5 6 7 8 tT END TRANSFER tI MSB LSB BIT 6 BIT 1 BIT 5 BIT 2 BIT 4 BIT 3 BIT 3 BIT 4 BIT 2 BIT 5 BIT 1 BIT 6 LSB MSB MINIMUM tL, tT, and tI = 1/2 SCK CYCLE Figure 15-6. Transmission Format 1 (CPHA = 1) MISO/MOSI MASTER SS SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3 Figure 15-7. Slave SS When CPHA = 1 MC68HC812A4 -- Rev. 3.0 270 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) Functional Description 15.6.5 SS Output In master mode only, the SS pin can function as a chip-select output for connection to the SS input of a slave. The master SS output automatically selects the slave by going low for each transmission and deselects the slave by going high during each idling state. Enable the SS output by setting the master mode bit, MSTR, the slave-select output enable bit, SSOE, and the data direction bit of the SS pin. MSTR and SSOE are in SPI control register 1. Table 15-1. SS Pin Configurations Control Bits DDRS7 0 0 1 1 SSOE 0 1 0 1 SS Pin Function Master Mode Slave-select input with mode-fault detection Reserved Slave-select input General-purpose output Slave-select output Slave Mode Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 271 Serial Peripheral Interface (SPI) 15.6.6 Single-Wire Operation Normally, the SPI operates as a 2-wire interface; it uses its MOSI and MISO pins for transmitting and receiving. In single-wire operation, a master SPI uses the MOSI pin for both receiving and transmitting. The MOSI pin becomes a master out, master in (MOMI) pin. The MISO pin is disconnected from the SPI and is available as a general-purpose port S I/O pin. A slave SPI in single-wire operation uses the MISO pin for both receiving and transmitting. The MISO pin becomes a slave in, slave out (SISO) pin. The MOSI pin is disconnected from the SPI and is available as a general-purpose I/O pin. Setting serial pin control bit 0, SPC0, configures the SPI for single-wire operation. The direction of the single-wire pin depends on its data direction bit. SERIAL OUT MASTER MODE SPI SERIAL IN MOMI DDRS5 PS4 GENERALPURPOSE I/O SERIAL IN SLAVE MODE SPI SERIAL OUT DDRS4 PS5 GENERALPURPOSE I/O SISO Figure 15-8. Single-Wire Operation (SPC0 = 1) MC68HC812A4 -- Rev. 3.0 272 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) SPI Register Descriptions and Reset Initialization 15.7 SPI Register Descriptions and Reset Initialization This section describes the SPI registers and reset initialization. 15.7.1 SPI Control Register 1 Address: $00D0 Bit 7 Read: SPIE Write: Reset: 0 0 0 0 0 1 0 0 SPE SWOM MSTR CPOL CPHA SSOE LSBF 6 5 4 3 2 1 Bit 0 Figure 15-9. SPI Control Register 1 (SP0CR1) Read: Anytime Write: Anytime SPIE -- SPI Interrupt Enable Bit SPIE enables the SPIF and MODF flags to generate interrupt requests. 1 = SPIF and MODF interrupt requests enabled 0 = SPIF and MODF interrupt requests disabled SPE -- SPI Enable Bit Setting the SPE bit enables the SPI and configures port S pins 7-4 for SPI functions. Clearing SPE puts the SPI in a disabled, low-power state. 1 = SPI enabled 0 = SPI disabled NOTE: When the MODF flag is set, SPE always reads as logic 0. Writing to SPI control register 1 is part of the mode fault recovery sequence. SWOM -- Port S Wired-OR Mode Bit SWOM disables the pullup devices on port S pins 7-4 so that they become open-drain outputs. 1 = Open-drain port S pin 7-4 outputs 0 = Normal push-pull port S pin 7-4 outputs Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 273 Serial Peripheral Interface (SPI) MSTR -- Master Mode Bit MSTR selects master mode operation or slave mode operation. 1 = Master mode 0 = Slave mode CPOL -- Clock Polarity Bit CPOL determines the logic state of the serial clock pin between transmissions. See Figure 15-4 and Figure 15-6. 1 = Active-high SCK 0 = Active-low SCK CPHA -- Clock Phase Bit CPHA determines whether transmission begins on the falling edge of the SS pin or on the first edge of the serial clock. See Figure 15-4 and Figure 15-6. 1 = Transmission at first SCK edge 0 = Transmission at falling SS edge SSOE -- Slave Select Output Enable Bit SSOE enables the output function of master SS pin when the DDRS7 bit is also set. 1 = SS output enabled 0 = SS output disabled LSBF -- LSB First Bit LSBF enables least-significant-bit-first transmissions. It does not affect the position of data in the SPI data register; reads and writes of the SPI data register always have the MSB in bit 7. 1 = Least-significant-bit-first transmission 0 = Most-significant-bit-first transmission MC68HC812A4 -- Rev. 3.0 274 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) SPI Register Descriptions and Reset Initialization 15.7.2 SPI Control Register 2 Address: $00D1 Bit 7 Read: Write: Reset: 0 0 0 0 1 0 0 0 0 6 0 5 0 4 0 PUPS RDS 3 2 1 0 SPC0 Bit 0 = Unimplemented Figure 15-10. SPI Control Register 2 (SP0CR2) Read: Anytime Write: Anytime PUPS -- Pullup Port S Bit Setting PUPS enables internal pullup devices on all port S input pins. If a pin is programmed as output, the pullup device becomes inactive. 1 = Pullups enabled 0 = Pullups disabled RDS -- Reduced Drive Port S Bit Setting RDS lowers the drive capability of all port S output pins for lower power consumption and less noise. 1 = Reduced drive 0 = Normal drive SPC0 -- Serial Pin Control Bit 0 SPC0 enables single-wire operation of the MOSI and MISO pins. Table 15-2. Single-Wire Operation Control Bits SPC0 MSTR 1 1 0 -- 0 1 General-purpose I/O Slave input Slave output DDRS5 0 1 DDRS4 -- MOSI Master input Master output Pins MISO General-purpose I/O Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 275 Serial Peripheral Interface (SPI) 15.7.3 SPI Baud Rate Register Address: $00D2 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 SPR2 SPR1 SPR0 2 1 Bit 0 = Unimplemented Figure 15-11. SPI Baud Rate Register (SP0BR) Read: Anytime Write: Anytime SPR2-SPR0 -- SPI Clock Rate Select Bits These bits select one of eight SPI baud rates as shown in Table 15-3. Reset clears SPR2-SPR0, selecting E-clock divided by two. Table 15-3. SPI Clock Rate Selection SPR[2:1:0] 000 001 010 011 100 101 110 111 E-Clock Divisor 2 4 8 16 32 64 128 256 Baud Rate (E-Clock = 4 MHz) 2.0 MHz 1.0 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz 15.6 kHz Baud Rate (E-Clock = 8 MHz) 4.0 MHz 2.0 MHz 1.0 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz MC68HC812A4 -- Rev. 3.0 276 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) SPI Register Descriptions and Reset Initialization 15.7.4 SPI Status Register Address: $00D3 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 SPIF 6 WCOL 5 0 4 MODF 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 15-12. SPI Status Register (SP0SR) Read: Anytime Write: Has no meaning or effect SPIF -- SPI Flag SPIF is set after the eighth serial clock cycle of a transmissson. SPIF generates an interrupt request if the SPIE bit in SPI control register 1 is set also. Clear SPIF by reading the SPI status register with SPIF set and then reading or writing to the SPI data register. 1 = Transfer complete 0 = Transfer not complete WCOL -- Write Collision Flag WCOL is set when a write to the SPI data register occurs during a data transfer. The byte being transferred continues to shift out of the shift register, and the data written during the transfer is lost. WCOL does not generate an interrupt request. WCOL can be read when the transfer in progress is complete. Clear WCOL by reading the SPI status register with WCOL set and then reading or writing to the SPI data register. 1 = Write collision 0 = No write collision Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 277 Serial Peripheral Interface (SPI) MODF -- Mode Fault Flag MODF is set if the PS7 pin goes to logic 0 when it is configured as the SS input of a master SPI (MSTR = 1 and DDR7 = 0). Clear MODF by reading the SPI status register with MODF set and then writing to SPI control register 1. 1 = Mode fault 0 = No mode fault NOTE: MODF is inhibited when the PS7 pin is configured as: * * The SS output, DDRS7 = 1 and SSOE = 1, or A general-purpose output, DDRS7 = 1 and SSOE = 0 15.7.5 SPI Data Register Address: $00D5 Bit 7 Read: Bit 7 Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 Figure 15-13. SPI Data Register (SP0DR) Read: Anytime; normally, only after SPIF flag set Write: Anytime a data transfer is not taking place The SPI data register is both the input and output register for SPI data. Reads are double-buffered but writes cause data to be written directly into the SPI shift register. The data registers of two SPIs can be connected through their MOSI and MISO pins to form a distributed 16-bit register. A transmission between the SPIs shifts the data eight bit positions, exchanging the data between the master and the slave. The slave can also be another simpler device that only receives data from the master or that only sends data to the master. MC68HC812A4 -- Rev. 3.0 278 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) External Pins 15.8 External Pins The SPI module has four I/O pins: * * * * MISO -- Master data in, slave data out MOSI -- Master data out, slave data in SCK -- Serial clock SS -- Slave select The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 15.8.1 MISO (Master In, Slave Out) In a master SPI, MISO is the data input. In a slave SPI, MISO is the data output. In a slave SPI, the MISO output pin is enabled only when its SS pin is at logic 0. To support a multiple-slave system, a logic 1 on the SS pin of a slave puts the MISO pin in a high-impedance state. 15.8.2 MOSI (Master Out, Slave In) In a master SPI, MOSI is the data output. In a slave SPI, MOSI is the data input. 15.8.3 SCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master SPI, the SCK pin is the clock output to the slave. In a slave MCU, the SCK pin is the clock input from the master. Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 279 Serial Peripheral Interface (SPI) 15.8.4 SS (Slave Select) The SS pin has multiple functions that depend on SPI configuration: * * * The SS pin of a slave SPI is always configured as an input and allows the slave to be selected for transmission. When the CPHA bit is clear, the SS pin signals the start of a transmission. The SS pin of a master SPI can be configured as a mode-fault input, a slave-select output, or a general-purpose output. - As a mode-fault input (MSTR = 1, DDRS7 = 0, SSOE = 0), the SS pin can detect multiple masters driving MOSI and SPSCK. - As a slave-select output (MSTR = 1, DDRS7 = 1, SSOE = 1), the SS pin can select slaves for transmission. - When MSTR = 1, DDRS7 = 1, and SSOE = 0, the SS pin is available as a general-purpose output. 15.9 Low-Power Options This section describes the three low-power modes: * * * Run mode Wait mode Stop mode 15.9.1 Run Mode Clearing the SPI enable bit, SPE, in SPI control register 1 reduces power consumption in run mode. SPI registers are still accessible when SPE is cleared, but clocks to the core of the SPI are disabled. 15.9.2 Wait Mode The SPI remains active in wait mode. Any enabled interrupt request from the SPI can bring the MCU out of wait mode. MC68HC812A4 -- Rev. 3.0 280 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) Interrupt Sources If SPI functions are not required during wait mode, reduce power consumption by disabling the SPI before executing the WAIT instruction. 15.9.3 Stop Mode For reduced power consumption, the SPI is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. Exiting stop mode by reset aborts any transmission in progress and resets the SPI. Entering stop mode during a transmission results in invalid data. 15.10 Interrupt Sources Table 15-4. SPI Interrupt Sources Interrupt Source Transmission complete Mode fault Flag SPIF SPIE MODF I bit $FFD8, $FFD9 Local Enable CCR Mask Vector Address 15.11 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7-PS0 are available for either general-purpose I/O or for SCI and SPI functions. See Section 13. Multiple Serial Interface (MSI). Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 281 Serial Peripheral Interface (SPI) 15.12 Synchronous Character Transmission using the SPI This program is intended to communicate with the HC11 on the UDLP1 board. It utilizes the SPI to transmit synchronously characters in a string to be displayed on the LCD display. The program must configure the SPI as a master, and non-interrupt driven. The slave peripheral is chip-selected with the SS line at low voltage level. Between 8 bit transfers the SS line is held high. Also the clock idles low and takes data on the rising clock edges. The serial clock is set not to exceed 100 kHz baud rate. 15.12.1 Equipment For this exercise, use the M68HC812A4EVB emulation board. 15.12.2 Code Listing NOTE: A comment line is deliminted by a semi-colon. If there is no code before comment, an ";" must be placed in the first column to avoid assembly errors. ;Equates for all registers INCLUDE 'EQUATES.ASM' ; User Variables ; Bit Equates ; ---------------------------------------------------------------------; MAIN PROGRAM ; ---------------------------------------------------------------------ORG $7000 ; 16K On-Board RAM, User code data area, ; ; start main program at $7000 MAIN: BSR INIT ; Subroutine to initialize SPI registers BSR TRANSMIT ; Subroutine to start transmission FINISH: BRA FINIS ; Finished transmitting all DATA MC68HC812A4 -- Rev. 3.0 282 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Serial Peripheral Interface (SPI) Synchronous Character Transmission using the SPI ; ---------------------------------------------------------------------;* SUBROUTINE INIT: ; ---------------------------------------------------------------------INIT: BSET PORTS,#$80 ; SET SS Line High to prevent glitch MOVB ; MOVB MOVB ; MOVB ; LDX LDAA LDAA BSET RTS #DATA SP0SR SP0DR SP0CR1,#$40 #$08,SP0CR2 #$07,SP0BR #$12,SP0CR1 #$E0,DDRS ; Configure PORT S input/ouput levels ; MOSI, SCK, SS* = ouput, MISO=Input ; Select serial clock baud rate < 100 KHz ; Configure SPI(SP0CR1): No SPI interrupts, ; MSTR=1, CPOL=0, CPHA=0 ; Config. PORTS output drivers to operate normally, ; and with active pull-up devices. ; Use X register as pointer to first character ; 1st step to clear SPIF Flag, Read SP0SR ; 2nd step to clear SPIF Flag, Access SP0DR ; Enable the SPI (SPE=1) ; Return from subroutine ; ---------------------------------------------------------------------;* TRANSMIT SUBROUTINE ; ---------------------------------------------------------------------TRANSMIT: LDAA 1,X+ ; Load Acc. with "NEW" character to send, Inc X BEQ DONE ; Detect if last character(0) has been transmitted ; ; If last char. branch to DONE, else BCLR PORTS,#$80 ; Assert SS Line to start X-misssion. STAA SP0DR ; Load Data into Data Reg.,X-mit. ; ; it is also the 2nd step to clear SPIF flag. FLAG: BRCLR SP0SR,#$80,FLAG ;Wait for flag. BSET PORTS,#$80 ; Disassert SS Line. BRA TRANSMIT ; Continue sending characters, Branch to TRANSMIT. DONE: RTS ; Return from subroutine ; ---------------------------------------------------------------------; TABLE OF DATA TO BE TRANSMITTED ; ---------------------------------------------------------------------DATA: DC.B 'Motorola' DC.B $0D,$0A ; Return (cr) ,Line Feed (LF) EOT: DC.B $00 ; Byte used to test end of data = EOT END ; End of program Advance Information MOTOROLA Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 283 Serial Peripheral Interface (SPI) MC68HC812A4 -- Rev. 3.0 284 Serial Peripheral Interface (SPI) Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 16. Analog-to-Digital Converter (ATD) 16.1 Contents 16.2 16.3 16.4 16.5 16.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 16.7 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .291 16.7.1 ATD Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .291 16.7.2 ATD Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .291 16.7.3 ATD Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .292 16.7.4 ADT Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .293 16.7.5 ATD Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . .294 16.7.6 ATD Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . .296 16.7.7 ATD Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 16.7.8 ATD Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.7.9 ATD Result Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 16.8 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 16.8.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 16.8.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 16.8.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 16.9 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 16.10 General-Purpose Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 16.11 Port AD Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 16.12 Using the ATD to Measure a Potentiometer Signal . . . . . . . .303 16.12.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 16.12.2 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 285 Analog-to-Digital Converter (ATD) 16.2 Introduction The analog-to-digital converter (ATD) is an 8-channel, 8-bit, multiplexed-input, successive-approximation analog-to-digital converter, accurate to 1 least significant bit (LSB). It does not require external sample and hold circuits because of the type of charge redistribution technique used. The ATD converter timing can be synchronized to the system P-clock. The ATD module consists of a 16-word (32-byte) memory-mapped control register block used for control, testing and configuration. 16.3 Features Features of the ATD module include: * * * * * * Eight multiplexed input channels Multiplexed-input successive approximation 8-bit resolution Single or continuous conversion Conversion complete flag with CPU interrupt request Selectable ATD clock MC68HC812A4 -- Rev. 3.0 286 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Block Diagram 16.4 Block Diagram RC DAC ARRAY AND COMPARATOR VRH VRL VDDA VSSA SAR CHANNEL 0 ANALOG MUX AND SAMPLE BUFFER AMP CHANNEL 1 MODE AND TIMING CONTROL CHANNEL 2 PORT AD DATA INPUT REGISTER CHANNEL 3 AN7/PAD7 AN6/PAD6 AN5/PAD5 AN4/PAD4 AN3/PAD3 AN2/PAD2 AN1/PAD1 AN0/PAD0 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CLOCK SELECT/PRESCALE Figure 16-1. ATD Block Diagram Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 287 Analog-to-Digital Converter (ATD) 16.5 Register Map NOTE: The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Bit 7 Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: 0 0 0 0 0 0 0 0 0 CCF7 0 CCF6 0 CCF5 0 CCF4 0 CCF3 0 CCF2 0 CCF1 0 CCF0 0 SCF 0 0 0 0 0 SMP1 0 S8CM 0 0 0 SMP0 0 SCAN 0 0 0 PRS4 0 MULT 0 0 0 PRS3 0 CD 0 0 0 PRS2 0 CC 0 CC2 0 ADPU 0 0 0 AFFC 0 0 0 AWAI 0 0 0 0 0 0 0 0 0 ASCIE 0 FRZ1 0 PRS1 0 CB 0 CC1 0 ASCIF 0 0 0 6 0 0 0 5 0 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 Bit 0 0 0 0 Addr. Register Name ATD Control Register 0 $0060 (ATDCTL0) See page 291. ATD Control Register 1 $0061 (ATDCTL1) See page 291. ATD Control Register 2 $0062 (ATDCTL2) See page 292. ATD Control Register 3 $0063 (ATDCTL3) See page 293. ATD Control Register 4 $0064 (ATDCTL4) See page 294. ATD Control Register 5 $0065 (ATDCTL5) See page 296. ATD Status Register 1 (ATDSTAT1) See page 298. ATD Status Register 2 (ATDSTAT2) See page 298. 0 0 0 0 0 0 0 FRZ0 0 PRS0 1 CA 0 CC0 $0066 $0067 = Unimplemented Figure 16-2. ATD I/O Register Summary (Sheet 1 of 3) MC68HC812A4 -- Rev. 3.0 288 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Register Map Addr. Register Name ATD Test Register 1 (ATDTEST1) See page 299. ATD Test Register 2 (ATDTEST2) See page 299. Port AD Data Input Register (PORTAD) See page 302. ATD Result Register 0 (ADR0H) See page 300. ATD Result Register 1 (ADR1H) See page 300. ATD Result Register 2 (ADR2H) See page 300. ATD Result Register 3 (ADR3H) See page 300. ATD Result Register 4 (ADR4H) See page 300. ATD Result Register 5 (ADR5H) See page 300. Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 SAR9 0 SAR1 0 PAD7 6 SAR8 0 SAR0 0 PAD6 5 SAR7 0 RST 0 PAD5 4 SAR6 0 TSTOUT 0 PAD4 3 SAR5 0 TST3 0 PAD3 2 SAR4 0 TST2 0 PAD2 1 SAR3 0 TST1 0 PAD1 Bit 0 SAR2 0 TST0 0 PAD0 $0068 $0069 $006F 0 0 ADRxH6 0 ADRxH5 0 ADRxH4 0 ADRxH3 0 ADRxH2 0 ADRxH1 0 ADRxH0 Read: ADRxH7 Write: Reset: Read: ADRxH7 Write: Reset: Read: ADRxH7 Write: Reset: Read: ADRxH7 Write: Reset: Read: ADRxH7 Write: Reset: Read: ADRxH7 Write: Reset: $0070 Indeterminate ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0 $0072 Indeterminate ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0 $0074 Indeterminate ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0 $0076 Indeterminate ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0 $0078 Indeterminate ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0 $007A Indeterminate = Unimplemented Figure 16-2. ATD I/O Register Summary (Sheet 2 of 3) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 289 Analog-to-Digital Converter (ATD) Addr. Register Name ATD Result Register 6 (ADR6H) See page 300. ATD Result Register 7 (ADR7H) See page 300. Bit 7 Read: ADRxH7 Write: Reset: Read: ADRxH7 Write: Reset: 6 ADRxH6 5 ADRxH5 4 ADRxH4 3 ADRxH3 2 ADRxH2 1 ADRxH1 Bit 0 ADRxH0 $007C Indeterminate ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0 $007E Indeterminate = Unimplemented Figure 16-2. ATD I/O Register Summary (Sheet 3 of 3) 16.6 Functional Description A single conversion sequence consists of four or eight conversions, depending on the state of the select 8-channel mode bit, S8CM, in ATD control register 5 (ATDCTL5). There are eight basic conversion modes. In the non-scan modes, the sequence complete flag, SCF, is set after the sequence of four or eight conversions has been performed and the ATD module halts. In the scan modes, the SCF flag is set after the first sequence of four or eight conversions has been performed, and the ATD module continues to restart the sequence. In both modes, the CCF flag associated with each register is set when that register is loaded with the appropriate conversion result. That flag is cleared automatically when that result register is read. The conversions are started by writing to the control registers. The ATD control register 4 selects the clock source and sets up the prescaler. Writes to the ATD control registers initiate a new conversion sequence. If a write occurs while a conversion is in progress, the conversion is aborted and ATD activity halts until a write to ATDCTL5 occurs. The ATD control register 5 selects conversion modes and conversion channel(s) and initiates conversions. MC68HC812A4 -- Rev. 3.0 290 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Registers and Reset Initialization A write to ATDCTL5 initiates a new conversion sequence. If a conversion sequence is in progress when a write occurs, the sequence is aborted and the SCF and CCF flags are cleared. 16.7 Registers and Reset Initialization This section describes the registers and reset initialization. 16.7.1 ATD Control Register 0 Address: $0060 Bit 7 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 16-3. ATD Control Register 0 (ATDCTL0) NOTE: Writing to this register aborts the current conversion sequence. 16.7.2 ATD Control Register 1 Address: $0061 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 16-4. ATD Control Register 1 (ATDCTL1) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 291 Analog-to-Digital Converter (ATD) 16.7.3 ATD Control Register 2 Address: $0062 Bit 7 Read: ADPU Write: Reset: 0 0 0 0 0 0 0 0 AFFC AWAI 6 5 4 0 3 0 2 0 ASCIE 1 Bit 0 ASCIF = Unimplemented Figure 16-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime except ASCIF flag, which is read-only NOTE: Writing to this register aborts the current conversion sequence. ADPU -- ATD Powerup Bit ADPU enables the clock signal to the ATD and powers up its analog circuits. 1 = ATD enabled 0 = ATD disabled NOTE: After ADPU is set, the ATD requires an analog circuit stabilization period. AFFC -- ATD Fast Flag Clear Bit When AFFC is set, writing to a result register (ADR0H-ADR7H) clears the associated CCF flag if it is set. When AFFC is clear, clearing a CCF flag requires a read of the status register followed by a read of the result register. 1 = Fast CCF clearing enabled 0 = Fast CCF clearing disabled AWAI -- ATD Stop in Wait Mode Bit ASWAI disables the ATD in wait mode for lower power consumption. 1 = ATD disabled in wait mode 0 = ATD enabled in wait mode MC68HC812A4 -- Rev. 3.0 292 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Registers and Reset Initialization ASCIE -- ATD Sequence Complete Interrupt Enable Bit ASCIE enables interrupt requests generated by the ATD sequence complete interrupt flag, ASCIF. 1 = ASCIF interrupt requests enabled 0 = ASCIF interrupt requests disabled ASCIF -- ATD Sequence Complete Interrupt Flag ASCIF is set when a conversion sequence is finished. If the ATD sequence complete interrupt enable bit, ASCIE, is also set, ASCIF generates an interrupt request. 1 = Conversion sequence complete 0 = Conversion sequence not complete NOTE: The ASCIF flag is set only when a conversion sequence is completed and ASCIE = 1 or interrupts on the analog-to-digital converter (ATD) module are enabled. 16.7.4 ADT Control Register 3 Address: $0063 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 FRZ1 FRZ0 1 Bit 0 = Unimplemented Figure 16-6. ATD Control Register 3 (ATDCTL3) FRZ1 and FRZ0 -- Freeze Bits The FRZ bits suspend ATD operation for background debugging. When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint is encountered. These two bits determine how the ATD responds when background debug mode becomes active. See Table 16-1. Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 293 Analog-to-Digital Converter (ATD) Table 16-1. ATD Response to Background Debug Enable FRZ1:FRZ0 00 01 10 11 ATD Response Continue conversions in active background mode Reserved Finish current conversion, then freeze Freeze when BDM is active 16.7.5 ATD Control Register 4 Address: $0064 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 1 0 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 16-7. ATD Control Register 4 (ATDCTL4) SMP1 and SMP0 -- Sample Time Select Bits These bits select one of four sample times after the buffered sample and transfer has occurred. Total conversion time depends on initial sample time (two ATD clocks), transfer time (four ATD clocks), final sample time (programmable, refer to Table 16-2), and resolution time (10 ATD clocks). Table 16-2. Final Sample Time Selection SMP[1:0] 00 01 10 11 Final Sample Time 2 ATD clock periods 4 ATD clock periods 8 ATD clock periods 16 ATD clock periods Total 8-Bit Conversion Time 18 ATD clock periods 20 ATD clock periods 24 ATD clock periods 32 ATD clock periods MC68HC812A4 -- Rev. 3.0 294 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Registers and Reset Initialization PRS[4:0] -- Prescaler Select Bits The prescaler divides the P-clock by the binary value written to PRS[4:0] plus one. To assure symmetry of the prescaler output, an additional divide-by-two circuit generates the ATD module clock. Clearing PRS[4:0] means the P-clock is divided only by the divide-by-two circuit. The reset state of PRS[4:0] is 00001, giving a total P-clock divisor of four, which is appropriate for nominal operation at 2 MHz. Table 16-3 shows the appropriate range of system clock frequencies for each P clock divisor. Table 16-3. Clock Prescaler Values PRS[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01xxx Do not use 1xxxx 1. Maximum conversion frequency is 2 MHz. Maximum P-clock divisor value becomes maximum conversion rate that can be used on this ATD module. 2. Minimum conversion frequency is 500 kHz. Minimum P-clock divisor value becomes minimum conversion rate that this ATD can perform. P-Clock Divisor 2 4 6 8 10 12 14 16 Max P-Clock(1) 4 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz Min P-Clock(2) 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 295 Analog-to-Digital Converter (ATD) 16.7.6 ATD Control Register 5 Address: $0065 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 S8CM SCAN MULT CD CC CB CA 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 16-8. ATD Control Register 5 (ATDCTL5) Read: Anytime Write: Anytime S8CM -- Select Eight Conversions Mode Bit S8CM selects conversion sequences of either eight or four conversions. 1 = Eight conversion sequences 0 = Four conversion sequences SCAN -- Continuous Channel Scan Bit SCAN selects a single conversion sequence or continuous conversion sequences. 1 = Continuous conversion sequences (scan mode) 0 = Single conversion sequence MULT -- Multichannel Conversion Bit Refer to Table 16-4. 1 = Conversions of sequential channels 0 = Conversions of a single input channel selected by the CD, CC, CB, and CA bits CD, CC, CB, and CA -- Channel Select Bits The channel select bits select the input to convert. LT = 1, the ATD sequencer selects MC68HC812A4 -- Rev. 3.0 296 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Registers and Reset Initialization Table 16-4. Multichannel Mode Result Register Assignment(1) S8CM CD CC CB 0* 0* 1* 1* 0* 0* 1* 1* 0* 0* 1* 1* 0* 1 0* 1* 1* 0* 0* 1* 1* 0* 0* 1* 1* 0* 0* 1* 1* 0* 1* 0* 1* 1* CA 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* 0* 1* Channel Input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH + VRL)/2 Test/Reserved AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH VRL (VRH + VRL)/2 Test/Reserved Result in ADRxH ADRxH0 ADRxH1 ADRxH2 ADRxH3 ADRxH0 ADRxH1 ADRxH2 ADRxH3 ADRxH0 ADRxH1 ADRxH2 ADRxH3 ADRxH0 ADRxH1 ADRxH2 ADRxH3 ADRxH0 ADRxH1 ADRxH2 ADRxH3 ADRxH4 ADRxH5 ADRxH6 ADRxH7 ADRxH0 ADRxH1 ADRxH2 ADRxH3 ADRxH4 ADRxH5 ADRxH6 ADRxH7 0 0 0 1 0 0 1 0* 1 0 1* 0* 1 1 1. When MULT = 1, bits with asterisks are don't care bits. The 4-conversion sequence from AN0 to AN3 or the 8-conversion sequence from AN0 to AN7 is completed in the order shown. When MULT = 0, the CD, CC, CB, and CA bits select one input channel. The conversion sequence is performed on this channel only. Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 297 Analog-to-Digital Converter (ATD) 16.7.7 ATD Status Registers Address: $0066 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 SCF 6 0 5 0 4 0 3 0 2 CC2 1 CC1 Bit 0 CC0 = Unimplemented Figure 16-9. ATD Status Register 1 (ATDSTAT1) Address: $0067 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 CCF7 6 CCF6 5 CCF5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 Bit 0 CCF0 = Unimplemented Figure 16-10. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Special mode only SCF -- Sequence Complete Flag In single conversion sequence mode (SCAN = 0 in ATDCTL5), SCF is set at the end of the conversion sequence. In continuous conversion mode (SCAN = 1 in ATDCTL5), SCF is set at the end of the first conversion sequence. Clear SCF by writing to control register 5 (ATDCTL5) to initiate a new conversion sequence. When the fast flag clear enable bit, AFFC, is set, SCF is cleared after the first result register is read. CC2-CC0 -- Conversion Counter Bits This 3-bit value reflects the value of the conversion counter pointer in either a 4-conversion or 8-conversion sequence. The pointer shows which channel is currently being converted and which result register will be written next. MC68HC812A4 -- Rev. 3.0 298 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Registers and Reset Initialization CCF7-CCF0 -- Conversion Complete Flags Each ATD channel has a CCF flag. A CCF flag is set at the end of the conversion on that channel. Clear a CCF flag by reading status register 1 with the flag set and then reading the result register of that channel. When the fast flag clear enable bit, AFFC, is set, reading the result register clears the associated CCF flag even if the status register has not been read. 16.7.8 ATD Test Registers Address: $0068 Bit 7 Read: SAR9 Write: Reset: 0 0 0 0 0 0 0 0 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 6 5 4 3 2 1 Bit 0 Figure 16-11. ATD Test Register 1 (ATDTEST1) Address: $0069 Bit 7 Read: SAR1 Write: Reset: 0 0 0 0 0 0 0 0 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 6 5 4 3 2 1 Bit 0 Figure 16-12. ATD Test Register 2 (ATDTEST2) Read: Special modes only Write: Special modes only The test registers control various special modes which are used during manufacturing. In the normal modes, reads of the test register return 0 and writes have no effect. Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 299 Analog-to-Digital Converter (ATD) SAR9-SAR0 -- SAR Data Bits Reads of this byte return the current value in the SAR. Writes to this byte change the SAR to the value written. Bits SAR9-SAR2 reflect the eight SAR bits used during the resolution process for an 8-bit result. SAR1 and SAR0 are reserved to allow future derivatives to increase ATD resolution to 10 bits. RST -- Reset Bit When set, this bit causes all registers and activity in the module to assume the same state as out of power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module to remain enabled). TSTOUT -- Multiplex Output of TST3-TST0 (factory use) TST3-TST0 -- Test Bits 3 to 0 (reserved) Selects one of 16 reserved factory testing modes 16.7.9 ATD Result Registers ADR0H: ADR1H: ADR2H: ADR3H: ADR4H: ADR5H: ADR6H: ADR7H: $0070 $0072 $0074 $0076 $0078 $007A $007C $007E Bit 7 Read: ADRxH7 Write: Reset: Indeterminate 6 ADRxH6 5 ADRxH5 4 ADRxH4 3 ADRxH3 2 ADRxH2 1 ADRxH1 Bit 0 ADRxH0 Figure 16-13. ATD Result Registers (ADR0H-ADR7H) Read: Anytime Write: Has no meaning or effect MC68HC812A4 -- Rev. 3.0 300 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Low-Power Options ADRxH7-ADRxH0 -- ATD Conversion Result Bits These bits contain the left justified, unsigned result from the ATD conversion. The channel from which this result was obtained depends on the conversion mode selected. These registers are always read-only in normal mode. 16.8 Low-Power Options This section describes the three low-power modes: * * * Run mode Wait mode Stop mode 16.8.1 Run Mode Clearing the ATD power-up bit, ADPU, in ATD control register 2 (ATDCTL2) reduces power consumption in run mode. ATD registers are still accessible, but the clock to the ATD is disabled and ATD analog circuits are powered down. 16.8.2 Wait Mode ATD operation in wait mode depends on the state of the ATD stop in wait bit, AWAI, in ATD control register 2 (ATDCTL2). * * If AWAI is clear, the ATD operates normally when the CPU is in wait mode If AWAI is set, the ATD clock is disabled and conversion continues unless ASWAI bit in ATDCTL2 register is set. 16.8.3 Stop Mode The ATD is inactive in stop mode for reduced power consumption. The STOP instruction aborts any conversion sequence in progress. Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 301 Analog-to-Digital Converter (ATD) 16.9 Interrupt Sources Table 16-5. SPI Interrupt Sources Interrupt Source Conversion sequence complete Flag ASCIF Local Enable ASCIE CCR Mask I bit Vector Address $FFD2, $FFD3 NOTE: The ASCIF flag is set only when a conversion sequence is completed and ASCIE = 1 or interrupts on the analog-to-digital converter (ATD) module are enabled. 16.10 General-Purpose Ports Port AD is an input-only port. When the ATD is enabled, port AD is the analog input port for the ATD. Setting the ATD power-up bit, ADPU, in ATD control register 2 enables the ATD. Port AD is available for general-purpose input when the ATD is disabled. Clearing the ADPU bit disables the ATD. 16.11 Port AD Data Register Address: $006F Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 PAD7 6 PAD6 5 PAD5 4 PAD4 3 PAD3 2 PAD2 1 PAD1 Bit 0 PAD0 = Unimplemented Figure 16-14. Port AD Data Input Register (PORTAD) Read: Anytime; reads return logic levels on the PAD pins Write: Has no meaning or effect PAD7-PAD0 -- Port AD Data Input Bits MC68HC812A4 -- Rev. 3.0 302 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Analog-to-Digital Converter (ATD) Using the ATD to Measure a Potentiometer Signal 16.12 Using the ATD to Measure a Potentiometer Signal This exercise allows the student to utilize the ATD on the HC12 to measure a potentiometer signal output routed from the UDLP1 board to the HC12 ATD pin PAD6. First the ATDCTL registers are initialized. A delay loop of 100 s is then executed. The resolution is set up followed by a conversion set up on channel 6. After waiting for the status bit to set, the result goes to the D accumulator. If the program is working properly, a different value should be found in the D accumulator as the left potentiometer is varied for each execution of the program. 16.12.1 Equipment For this exercise, use the M68HC812A4EVB emulation board. 16.12.2 Code Listing NOTE: A comment line is deliminted by a semi-colon. If there is no code before comment, an ";" must be placed in the first column to avoid assembly errors. ; ---------------------------------------------------------------------; MAIN PROGRAM ; ---------------------------------------------------------------------ORG $7000 ; 16K On-Board RAM, User code data area, ; start main program at $7000 MAIN: DONE: BSR BSR BRA INIT CONVERT DONE ; Branch to INIT subroutine to Initialize ATD ; Branch to CONVERT Subroutine for conversion ; Branch to Self, Convenient place for breakpoint ; ---------------------------------------------; Subroutine INIT: Initialize ATD ; ; ---------------------------------------------INIT: LDAA #$80 ; Allow ATD to function normally, STAA ATDCTL2 ; ATD Flags clear normally & disable interrupts BSR LDAA STAA LDAA STAA RTS DELAY #$00 ATDCTL3 #$01 ATDCTL4 ; Delay (100 uS) for WAIT delay time. ; Select continue conversion in BGND Mode ; Ignore FREEZE in ATDCTL3 ; Select Final Sample time = 2 A/D clocks ; Prescaler = Div by 4 (PRS4:0 = 1) ; Return from subroutine Advance Information MOTOROLA Analog-to-Digital Converter (ATD) MC68HC812A4 -- Rev. 3.0 303 Analog-to-Digital Converter (ATD) ; ; ; ; ; ; ; ; ---------------------------------------------Subroutine CONVERT: ; ---------------------------------------------Set-up ATD, make single conversion and store the result to a memory location. Configure and start A/D conversion Analog Input Signal: On PORT AD6 Convert: using single channel, non-continuous The result will be located in ADR2H CONVERT: LDAA ; STAA ; WTCONV: BRCLR LDD ; BRA RTS CONVERT ATDCTL5 #$06 ; ; ; ; Initializes ATD SCAN=0,MULT=0, PAD6, Write Clears Flag 4 conversions on a Single Conversion sequence, ATDSTATH,#$80,WTCONV ; Wait for Sequence Complete Flag ADR2H ; Loads conversion result(ADR2H) ; into Accumulator ; Continuously updates results ; Return from subroutine ;* ------------------------------;* Subroutine DELAY 100 uS * ;* ------------------------------; Delay Required for ATD converter to Stabilize (100 uSec) LDAA DECA BNE RTS END #$C8 DELAY ; ; ; ; Load Accumulator with "100 uSec delay value" Decrement ACC Branch if not equal to Zero Return from subroutine DELAY: ; End of program MC68HC812A4 -- Rev. 3.0 304 Analog-to-Digital Converter (ATD) Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 17. Development Support 17.1 Contents 17.2 17.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 17.4 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . .307 17.4.1 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 17.4.2 Enabling BDM Firmware Commands . . . . . . . . . . . . . . . . .311 17.4.3 BDM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 17.5 BDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.5.1 BDM Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.5.1.1 Hardware Command . . . . . . . . . . . . . . . . . . . . . . . . . . .314 17.5.1.2 Firmware Command. . . . . . . . . . . . . . . . . . . . . . . . . . . .315 17.5.2 BDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 17.5.3 BDM Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 17.5.4 BDM Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .318 17.5.5 BDM CCR Holding Register . . . . . . . . . . . . . . . . . . . . . . . .319 17.6 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 17.2 Introduction This section describes: * * * * Instruction queue Queue tracking signals Background debug mode (BDM) Instruction tagging Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 305 Development Support 17.3 Instruction Queue The CPU12 instruction queue provides at least three bytes of program information to the CPU when instruction execution begins. The CPU12 always completely finishes executing an instruction before beginning to execute the next instruction. Status signals IPIPE[1:0] provide information about data movement in the queue and indicate when the CPU begins to execute instructions. This makes it possible to monitor CPU activity on a cycle-by-cycle basis for debugging. Information available on the IPIPE[1:0] pins is time multiplexed. External circuitry can latch data movement information on rising edges of the E-clock signal; execution start information can be latched on falling edges. Table 17-1 shows the meaning of data on the pins. Table 17-1. IPIPE Decoding Data Movement -- IPIPE[1:0] Captured at Rising Edge of E Clock(1) IPIPE[1:0] 0:0 0:1 1:0 1:1 Mnemonic -- LAT ALD ALL No movement Latch data from bus Advance queue and load from bus Advance queue and load from latch Meaning Execution Start -- IPIPE[1:0] Captured at Falling Edge of E Clock(2) IPIPE[1:0] 0:0 0:1 1:0 1:1 Mnemonic -- INT SEV SOD No start Start interrupt sequence Start even instruction Start odd instruction Meaning 1. Refers to data that was on the bus at the previous E falling edge. 2. Refers to bus cycle starting at this E falling edge. MC68HC812A4 -- Rev. 3.0 306 Development Support Advance Information MOTOROLA Development Support Background Debug Mode (BDM) Program information is fetched a few cycles before it is used by the CPU. To monitor cycle-by-cycle CPU activity, it is necessary to externally reconstruct what is happening in the instruction queue. Internally, the MCU only needs to buffer the data from program fetches. For system debug, it is necessary to keep the data and its associated address in the reconstructed instruction queue. The raw signals required for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and status signals IPIPE[1:0]. The instruction queue consists of two 16-bit queue stages and a holding latch on the input of the first stage. To advance the queue means to move the word in the first stage to the second stage and move the word from either the holding latch or the data bus input buffer into the first stage. To start even (or odd) instruction means to execute the opcode in the high-order (or low-order) byte of the second stage of the instruction queue. 17.4 Background Debug Mode (BDM) Background debug mode (BDM) is used for: * * * * System development In-circuit testing Field testing Programming BDM is implemented in on-chip hardware and provides a full set of debug options. Because BDM control logic does not reside in the CPU, BDM hardware commands can be executed while the CPU is operating normally. The control logic generally uses CPU dead cycles to execute these commands, but can steal cycles from the CPU when necessary. Other BDM commands are firmware based and require the CPU to be in active background mode for execution. While BDM is active, the CPU executes a firmware program located in a small on-chip ROM that is available in the standard 64-Kbyte memory map only while BDM is active. Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 307 Development Support The BDM control logic communicates with an external host development system serially, via the BKGD pin. This single-wire approach minimizes the number of pins needed for development support. 17.4.1 BDM Serial Interface The BDM serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 E-clock cycles per bit (nominal speed). The interface times out if 512 E-clock cycles occur between falling edges from the host. The hardware clears the command register when this timeout occurs. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to MCU clocks but asynchronous to the external host. The internal clock signal is shown for reference in counting cycles. Figure 17-1 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target M68HC12 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target E cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Since the target does not drive the BKGD pin during this period, there is no need to treat the line as an open-drain signal during host-to-target transmissions. MC68HC812A4 -- Rev. 3.0 308 Development Support Advance Information MOTOROLA Development Support Background Debug Mode (BDM) E CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT TIME TARGET SENSES BIT LEVEL Figure 17-1. BDM Host-to-Target Serial Bit Timing Figure 17-2 shows the host receiving a logic 1 from the target MC68HC812A4 MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target E cycles). The host must release the low drive before the target MCU drives a brief active-high speed-up pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. Figure 17-3 shows the host receiving a logic 0 from the target MC68HC812A4 MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target MC68HC812A4 finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 309 Development Support E-CLOCK TARGET MCU HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEED-UP PULSE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN HIGH-IMPEDANCE 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 17-2. BDM Target-to-Host Serial Bit Timing (Logic 1) E-CLOCK TARGET MCU HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME SPEED-UP PULSE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 17-3. BDM Target-to-Host Serial Bit Timing (Logic 0) MC68HC812A4 -- Rev. 3.0 310 Development Support Advance Information MOTOROLA Development Support Background Debug Mode (BDM) 17.4.2 Enabling BDM Firmware Commands BDM is available in all operating modes, but must be made active before firmware commands can be executed. BDM is enabled by setting the ENBDM bit in the BDM STATUS register via the single wire interface (using a hardware command; WRITE_BD_BYTE at $FF01). BDM must then be activated to map BDM registers and ROM to addresses $FF00 to $FFFF and to put the MCU in active background mode. After the firmware is enabled, BDM can be activated by the hardware BACKGROUND command, by the BDM tagging mechanism, or by the CPU BGND instruction. An attempt to activate BDM before firmware has been enabled causes the MCU to resume normal instruction execution after a brief delay. BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND command, but tags activate BDM before a tagged instruction is executed. In special single-chip mode, background operation is enabled and active immediately out of reset. This active case replaces the M68HC11 boot function and allows programming a system with blank memory. While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The BDM control logic uses these registers which can be read anytime by BDM logic, not user programs. Refer to 17.5 BDM Registers for detailed descriptions. Some on-chip peripherals have a BDM control bit which allows suspending the peripheral function during BDM. For example, if the timer control is enabled, the timer counter is stopped while in BDM. Once normal program flow is continued, the timer counter is re-enabled to simulate real-time operations. 17.4.3 BDM Commands All BDM command opcodes are eight bits long and can be followed by an address and/or data, as indicated by the instruction. These commands do not require the CPU to be in active BDM mode for execution. Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 311 Development Support The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle. For data read commands, the host must insert this delay between sending the address and attempting to read the data. BDM logic retains control of the internal buses until a read or write is completed. If an operation can be completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation requires multiple cycles, CPU clocks are frozen until the operation is complete. The CPU must be in background mode to execute commands that are implemented in the BDM ROM. The BDM ROM is located at $FF20 to $FFFF while BDM is active. There are also seven bytes of BDM registers which are located at $FF00 to $FF06 while BDM is active. The CPU executes code from this ROM to perform the requested operation. These commands are shown in Table 17-2 and Table 17-3. Table 17-2. BDM Commands Implemented in Hardware Command BACKGROUND READ_BD_BYTE Opcode (Hex) 90 E4 Data None 16-bit address 16-bit data out Description Enter background mode, if firmware is enabled. Read from memory with BDM in map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte FF01, READ_BD_BYTE $FF01. Running user code; BGND 0000 0000 (out) instruction is not allowed STATUS(1) E4 FF01, 1000 0000 (out) READ_BD_BYTE $FF01. BGND instruction is allowed. FF01, READ_BD_BYTE $FF01. Background mode active, 1100 0000 (out) waiting for single wire serial command READ_BD_WORD EC 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data in Read from memory with BDM in map (may steal cycles if external access); must be aligned access Read from memory with BDM out of map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte Read from memory with BDM out of map (may steal cycles if external access); must be aligned access Write to memory with BDM in map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte Advance Information Development Support MOTOROLA READ_BYTE E0 READ_WORD E8 WRITE_BD_BYTE C4 MC68HC812A4 -- Rev. 3.0 312 Development Support Background Debug Mode (BDM) Table 17-2. BDM Commands Implemented in Hardware (Continued) Command ENABLE_ FIRMWARE(2) Opcode (Hex) Data FF01, 1xxx xxxx (in) 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in Description Write byte $FF01, set the ENBDM bit. This allows execution of commands which are implemented in firmware. Typically, read STATUS, OR in the MSB, write the result back to STATUS. Write to memory with BDM in map (may steal cycles if external access); must be aligned access Write to memory with BDM out of map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte Write to memory with BDM out of map (may steal cycles if external access); must be aligned access C4 WRITE_BD_WORD CC WRITE_BYTE C0 WRITE_WORD C8 1. STATUS command is a specific case of the READ_BD_BYTE command. 2. ENABLE_FIRMWARE is a specific case of the WRITE_BD_BYTE command. Table 17-3. BDM Firmware Commands Command READ_NEXT READ_PC READ_D READ_X READ_Y READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO TRACE1 TAGGO Opcode (Hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 10 18 Data 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in None None None Description X = X + 2; read next word pointed to by X Read program counter Read D accumulator Read X index register Read Y index register Read stack pointer X = X + 2; write next word pointed to by X Write program counter Write D accumulator Write X index register Write Y index register Write stack pointer Go to user program Execute one user instruction, then return to BDM Enable tagging and go to user program Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 313 Development Support 17.5 BDM Registers Seven BDM registers are mapped into the standard 64-Kbyte address space when BDM is active. The registers can be accessed with the hardware READ_BD and WRITE_BD commands, but must not be written during BDM operation. Most users are only interested in the STATUS register at $FF01; other registers are for use only by BDM firmware and logic. The instruction register is discussed for two conditions: * * When a hardware command is executed When a firmware command is executed 17.5.1 BDM Instruction Register This section describes the BDM instruction register under hardware command and firmware command. 17.5.1.1 Hardware Command Address: $FF00 Bit 7 Read: H/F Write: Reset: 0 0 0 0 0 0 0 0 DATA R/W BKGND W/B BD/U 0 0 6 5 4 3 2 1 Bit 0 Figure 17-4. BDM Instruction Register (INSTRUCTION) The bits in the BDM instruction register have the following meanings when a hardware command is executed. H/F -- Hardware/Firmware Flag 1 = Hardware instruction 0 = Firmware instruction DATA -- Data Flag 1 = Data included in command 0 = No data MC68HC812A4 -- Rev. 3.0 314 Development Support Advance Information MOTOROLA Development Support BDM Registers R/W -- Read/Write Flag 0 = Write 1 = Read BKGND -- Hardware Request Bit to Enter Active Background Mode 1 = Hardware background command (INSTRUCTION = $90) 0 = Not a hardware background command W/B -- Word/Byte Transfer Flag 1 = Word transfer 0 = Byte transfer BD/U -- BDM Map/User Map Flag Indicates whether BDM registers and ROM are mapped to addresses $FF00 to $FFFF in the standard 64-Kbyte address space. Used only by hardware read/write commands. 1 = BDM resources in map 0 = BDM resources not in map 17.5.1.2 Firmware Command Address: $FF00 Bit 7 Read: H/F Write: Reset: 0 0 0 0 0 0 0 0 DATA R/W TTAGO REGN 6 5 4 3 2 1 Bit 0 Figure 17-5. BDM Instruction Register (INSTRUCTION) The bits in the BDM instruction register have the following meanings when a firmware command is executed. H/F -- Hardware/Firmware Flag 1 = Hardware control logic 0 = Firmware control logic DATA -- Data Flag 1 = Data included in command 0 = No data Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 315 Development Support R/W -- Read/Write Flag 1 = Read 0 = Write TTAGO -- Trace, Tag, and Go Field Table 17-4. TTAGO Decoding TTAGO Value 00 01 10 11 Instruction -- GO TRACE1 TAGGO REGN -- Register/Next Field Indicates which register is being affected by a command. In the case of a READ_NEXT or WRITE_NEXT command, index register X is pre-incremented by 2 and the word pointed to by X is then read or written. Table 17-5. REGN Decoding REGN Value 000 001 010 011 100 101 110 111 Instruction -- -- READ/WRITE NEXT PC D X Y SP MC68HC812A4 -- Rev. 3.0 316 Development Support Advance Information MOTOROLA Development Support BDM Registers 17.5.2 BDM Status Register Address: $FF01 Bit 7 Read: ENBDM Write: Reset: Single-chip peripheral: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EDMACT ENTAG SDV TRACE 0 0 0 6 5 4 3 2 1 Bit 0 Figure 17-6. BDM Status Register (STATUS) This register can be read or written by BDM commands or firmware. ENBDM -- Enable BDM Bit (permit active background debug mode) 1 = BDM can be made active to allow firmware commands 0 = BDM cannot be made active (hardware commands still allowed). BDMACT -- Background Mode Active Status Bit 1 = BDM active and waiting for serial commands 0 = BDM not active ENTAG -- Instruction Tagging Enable Bit Set by the TAGGO instruction and cleared when BDM is entered. 1 = Tagging active (BDM cannot process serial commands while tagging is active.) 0 = Tagging not enabled or BDM active SDV -- Shifter Data Valid Bit Shows that valid data is in the serial interface shift register. Used by firmware-based instructions. 1 = Valid data 0 = No valid data TRACE -- Asserted by the TRACE1 Instruction Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 317 Development Support 17.5.3 BDM Shift Register Address: $FF02 Bit 7 Read: Write: Reset: S15 0 6 S14 0 5 S13 0 4 S12 0 3 S11 0 2 S10 0 1 S9 0 Bit 0 S8 0 Address: $FF03 Bit 7 Read: Write: Reset: S7 0 6 S6 0 5 S5 0 4 S4 0 3 S3 0 2 S2 0 1 S1 0 Bit 0 S0 0 Figure 17-7. BDM Shift Register (SHIFTER) This 16-bit register contains data being received or transmitted via the serial interface. 17.5.4 BDM Address Register Address: $FF04 Bit 7 Read: Write: Reset: A15 0 6 A14 0 5 A13 0 4 A12 0 3 A11 0 2 A10 0 1 A9 0 Bit 0 A8 0 Address: $FF05 Bit 7 Read: Write: Reset: A7 0 6 A6 0 5 A5 0 4 A4 0 3 A3 0 2 A2 0 1 A1 0 Bit 0 A0 0 Figure 17-8. BDM Address Register (ADDRESS) This 16-bit register is temporary storage for BDM hardware and firmware commands. MC68HC812A4 -- Rev. 3.0 318 Development Support Advance Information MOTOROLA Development Support Instruction Tagging 17.5.5 BDM CCR Holding Register Address: $FF06 Bit 7 Read: CCR7 Write: Reset: 0 0 0 0 0 0 0 0 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 6 5 4 3 2 1 Bit 0 Figure 17-9. BDM CCR Holding Register (CCRSAV) This register preserves the content of the CPU12 CCR while BDM is active. 17.6 Instruction Tagging The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real time or from trace history that was captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a specific instruction, because execution has already begun by the time an operation is visible outside the MCU. A separate instruction tagging mechanism is provided for this purpose. Executing the BDM TAGGO command configures two MCU pins for tagging. Tagging information is latched on the falling edge of ECLK along with program information as it is fetched. Tagging is allowed in all modes. Tagging is disabled when BDM becomes active and BDM serial commands cannot be processed while tagging is active. TAGHI is a shared function of the BKGD pin. TAGLO is a shared function of the PE3/LSTRB pin, a multiplexed I/O pin. For 1/4 cycle before and after the rising edge of the E-clock, this pin is the LSTRB driven output. TAGLO and TAGHI inputs are captured at the falling edge of the E-clock. A logic 0 on TAGHI and/or TAGLO marks (tags) the instruction on the high and/or low byte of the program word that was on the data bus at the same falling edge of the E-clock. Advance Information MOTOROLA Development Support MC68HC812A4 -- Rev. 3.0 319 Development Support The tag follows the information in the queue as the queue is advanced. When a tagged instruction reaches the head of the queue, the CPU enters active background debugging mode rather than executing the instruction. This is the mechanism by which a development system initiates hardware breakpoints. MC68HC812A4 -- Rev. 3.0 320 Development Support Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 18. Electrical Characteristics 18.1 Contents 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .323 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .324 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 ATD Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 ATD DC Electrical Characteristcs. . . . . . . . . . . . . . . . . . . . . .326 Analog Converter Operating Characteristics . . . . . . . . . . . . .327 18.10 ATD AC Operating Characteristics . . . . . . . . . . . . . . . . . . . . .328 18.11 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 18.12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 18.13 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 18.14 Non-Multiplexed Expansion Bus Timing . . . . . . . . . . . . . . . . .334 18.15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 321 Electrical Characteristics 18.2 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 18.5 DC Electrical Characteristics for guaranteed operating conditions. Rating Symbol VDD VDDA VDDX VIn IIn TSTG VDD-VDDX Value Unit Supply voltage -0.3 to +6.5 V Input voltage Maximum current per pin excluding VDD and VSS Storage temperature VDD differential voltage -0.3 to +6.5 25 -55 to +150 6.5 V mA C V NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIn and VOut be constrained to the range VSS (VIn or VOut) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD). MC68HC812A4 -- Rev. 3.0 322 Electrical Characteristics Advance Information MOTOROLA Electrical Characteristics Functional Operating Range 18.3 Functional Operating Range Rating Operating temperature range MC68HC812A4PV8 MC68HC812A4CPV8 MC68HC812A4VPV8 MC68HC812A4MPV8 Operating voltage range Symbol Value TL to TH 0 to +70 -40 to +85 -40 to +105 -40 to +125 5.0 10% Unit TA C VDD V 18.4 Thermal Characteristics Characteristic Average junction temperature Ambient temperature Package thermal resistance (junction-to-ambient) 112-pin thin quad flat pack (TQFP) Symbol TJ TA JA Value TA + (PD x JA) User-determined 39 PINT + PI/O or K ------------------------T J + 273C Unit C C C/W Total power dissipation(1) PD W Device internal power dissipation I/O pin power dissipation(2) A constant(3) PINT PI/O K IDD x VDD User-determined PD x (TA + 273 C) + JA x PD2 W W W/C 1. This is an approximate value, neglecting PI/O. 2. For most applications, PI/O PINT and can be neglected. 3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value of K to solve for PD and TJ iteratively for any value of TA. Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 323 Electrical Characteristics 18.5 DC Electrical Characteristics Characteristic(1) Input high voltage, all inputs Input low voltage, all inputs Output high voltage, all I/O and output pins Normal drive strength IOH = -10.0 A IOH = -0.8 mA Reduced drive strength IOH = -4.0 A IOH = -0.3 mA Output low voltage, all I/O and output pins, normal drive strength IOL = 10.0 A IOL = 1.6 mA EXTAL, PAD[7:0], VRH, VRL, VFP, XIRQ, reduced drive strength IOL = 3.6 A IOL = 0.6 mA Input leakage current(2) all input pins VIn = VDD or VSS -- VRL, VRH, PAD6-PAD0 VIn = VDD or VSS -- IRQ VIn = VDD or VSS -- PAD7 Three-state leakage, I/O ports, BKGD, and RESET Input capacitance All input pins and ATD pins (non-sampling) ATD pins (sampling) All I/O pins Output load capacitance All outputs except PS7-PS4 PS7-PS4 Active pullup, pulldown current IRQ, XIRQ, DBE, ECLK, LSTRB, R/W, and BKGD Ports A, B, C, D, F, G, H, J, P, S, and T RAM standby voltage, power down RAM standby current Symbol VIH VIL Min 0.7 x VDD VSS-0.3 Max VDD + 0.3 0.2 x VDD Unit V V VOH VDD - 0.2 VDD - 0.8 VDD - 0.2 VDD - 0.8 -- -- -- -- VSS +0.2 VSS +0.4 VSS +0.2 VSS +0.4 1 10 10 2.5 10 15 20 90 200 500 -- 10 V VOL -- -- -- -- V IIn -- -- -- -- -- -- -- -- -- 50 1.5 -- A IOZ A CIn pF CL pF IAPU VSB ISB A V A 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted 2. Specification is for parts in the -40 to +85 C range. Higher temperature ranges will result in increased current leakage. MC68HC812A4 -- Rev. 3.0 324 Electrical Characteristics Advance Information MOTOROLA Electrical Characteristics Supply Current 18.6 Supply Current Characteristic(1) Maximum total supply current Run Single-chip mode Expanded mode Wait, all peripheral functions shut down Single-chip mode Expanded mode Stop, single-chip mode, no clocks -40 C to +85 C +85 C to +105 C +105 C to +125 C Maximum power dissipation(2) Single-chip mode Expanded mode Symbol 8 MHz Typical 2 MHz 4 MHz 8 MHz Unit IDD 30 47 WIDD 7 8 <1 < 10 < 25 54 76 15 25 1.5 4 10 25 50 62 90 25 40 4 5 10 25 50 54 76 40 65 8 10 10 25 50 62 90 mA mA mA mA A A A mW mW SIDD PD 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted 2. Includes IDD and IDDA 18.7 ATD Maximum Ratings ` Characteristic ATD reference voltage VRH VDDA VRL VSSA VSS differential voltage VDD differential voltage VREF differential voltage Reference to supply differential voltage Symbol VRH VRL |VSS-VSSA| |VDD-VDDA| VDD-VDDX |VRH-VRL| |VRH-VDDA| |VRL-VSSA| Value -0.3 to +6.5 -0.3 to +6.5 0.1 6.5 6.5 6.5 6.5 6.5 Units V V V V V Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 325 Electrical Characteristics 18.8 ATD DC Electrical Characteristcs Characteristic(1) Analog supply voltage Analog supply current, normal operation Reference voltage, low Reference voltage, high VREF differential reference voltage(2) Input voltage(3) Input current, off channel(4) Reference supply current Input capacitance Not Sampling Sampling Symbol VDDA IDDA VRL VRH VRH-VRL VINDC IOFF IREF CINN CINS Min 4.5 -- VSSA VDDA/2 4.5 VSSA -- -- Max 5.5 1.0 VDDA/2 VDDA 5.5 VDDA 100 250 Unit V mA V V V V nA A pF -- -- 10 15 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, ATD clock = 2 MHz, unless otherwise noted 2. Accuracy is guaranteed at VRH - VRL = 5.0 Vdc 10%. 3. To obtain full-scale, full-range results, VSSA VRL VINDC VRH VDDA. 4. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10 C decrease from maximum temperature. MC68HC812A4 -- Rev. 3.0 326 Electrical Characteristics Advance Information MOTOROLA Electrical Characteristics Analog Converter Operating Characteristics 18.9 Analog Converter Operating Characteristics Characteristic(1) 8-bit resolution(2) Differential non-linearity(3) Integral non-linearity(3) Absolute error(3),(4) 2, 4, 8, and 16 ATD sample clocks Maximum source impedance Symbol 2 counts DNL INL AE RS Min -- -0.5 -1 -2 -- Typical 24 -- -- -- 20 Max -- +0.5 +1 +2 See note(5) Unit mV count count count k 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, ATD clock = 2 MHz, unless otherwise noted 2. VRH-VRL 5.12 V; VDDA--VSSA = 5.12 V 3. At VREF = 5.12 V, one 8-bit count = 20 mV. 4. 8-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mv) inherent quantization error and 1/2 count (10 mV) circuit (differential, integral, and offset) error. 5. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result value due to junction leakage is expressed in voltage (VERRJ): VERRJ = RS x IOFF where IOFF is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of ATD clock speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge pump leakage is computed as follows: VERRJ = .25 pF x VDDA x RS x ATDCLK/(8 x number of channels) Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 327 Electrical Characteristics 18.10 ATD AC Operating Characteristics Characteristic(1) ATD operating clock frequency Conversion time per channel 0.5 MHz fATDCLK 2 MHz 18 ATD clocks 32 ATD clocks Stop recovery time VDDA = 5.0 V Symbol fATDCLK Min 0.5 Max 2.0 Unit MHz tCONV 8.0 15.0 -- 32.0 60.0 50 s tSR s 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, ATD clock = 2 MHz, unless otherwise noted 18.11 EEPROM Characteristics Characteristic(1) Minimum programming clock frequency(2) Programming time Clock recovery time following STOP, to continue programming Erase time Write/erase endurance Data retention Symbol fPROG tPROG tCRSTOP tErase -- -- Min 1.0 -- -- -- 10,000 10 Typical -- -- -- -- 30,000(3) -- Max -- 10 tPROG+ 1 10 -- -- Unit MHz ms ms ms cycles years 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted 2. RC oscillator must be enabled if programming is desired and fSYS < fPROG. 3. If average TH is below 85 C MC68HC812A4 -- Rev. 3.0 328 Electrical Characteristics Advance Information MOTOROLA Electrical Characteristics Control Timing 18.12 Control Timing 8.0 MHz Characteristic Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time tPCSU = tcyc/2 + 30 Reset input pulse width To guarantee external reset vector Minimum input time (can be pre-empted by internal reset) Mode programming setup time Mode programming hold time Interrupt pulse width, IRQ, edge-sensitive mode, KWU PWIRQ = 2 tcyc + 20 Wait recovery startup time Timer pulse width, input capture pulse accumulator input PWTIM = 2 tcyc + 20 Symbol Min fo tcyc fXTAL 2 fo tPCSU dc 125 -- dc 82 Max 5.0 -- 16.0 16.0 -- MHz ns MHz MHz ns Unit PWRSTL tMPS tMPH PWIRQ tWRS PWTIM 32 2 4 10 TBD -- TBD -- -- -- -- -- 4 -- tcyc tcyc ns ns tcyc ns PT[7:0](1) PWTIM PT[7:0](2) PT7(1) PWPA PT7(2) Notes: 1. Rising edge-sensitive input 2. Falling edge-sensitive input Figure 18-1. Timer Inputs Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 329 Electrical Characteristics MC68HC812A4 -- Rev. 3.0 VDD EXTAL 4098 tcyc ECLK tPCSU PWRSTL RESET tMPS MODA, MODB 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC tMPH INTERNAL ADDRESS FFFE FFFE FREE FFFE FFFE FFFE FREE Note: Reset timing is subject to change. 330 Electrical Characteristics MOTOROLA Figure 18-2. POR and External Reset Timing Diagram Advance Information MOTOROLA Electrical Characteristics 331 Advance Information INTERNAL CLOCKS IRQ1 PWIRQ IRQ or XIRQ tSTOPDELAY(3) ECLK SP-6 SP-8 SP-9 FREE FREE OPT FETCH 1ST EXEC ADDRESS4 Resume program with instruction which follows the STOP instruction. ADDRESS5 SP-6 SP-8 SP-9 FREE VECTOR FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Notes: 1. Edge-sensitive IRQ pin (IRQE bit = 1) 2. Level-sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 tcyc if DLY = 0. 4. XIRQ with X bit in CCR = 1. 5. IRQ or (XIRQ with X bit in CCR = 0) MC68HC812A4 -- Rev. 3.0 Figure 18-3. STOP Recovery Timing Diagram Electrical Characteristics Control Timing Electrical Characteristics MC68HC812A4 -- Rev. 3.0 Advance Information 332 Electrical Characteristics MOTOROLA ECLK tPCSU IRQ, XIRQ, OR INTERNAL INTERRUPTS tWRS ADDRESS SP - 2 SP - 4 SP - 6 . . . SP - 9 SP - 9 SP - 9. . . SP - 9 SP - 9 VECTOR ADDRESS FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC PC, IY, IX, B:A, , CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. Figure 18-4. WAIT Recovery Timing Diagram ECLK tPCSU IRQ(1) PWIRQ IRQ(2), XIRQ, OR INTERNAL INTERRUPT ADDRESS VECTOR ADDR DATA VECT PC PROG FETCH R/W Notes: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) IY IX PROG FETCH B:A CCR PROG FETCH SP - 2 1ST PIPE SP - 4 SP - 6 2ND PIPE SP - 8 SP - 9 3RD PIPE 1ST EXEC Figure 18-5. Interrupt Timing Diagram Electrical Characteristics Peripheral Port Timing 18.13 Peripheral Port Timing 5.0 MHz Characteristic Frequency of operation (E-clock frequency) E-clock period Peripheral data setup time, MCU read of ports tPDSU = tcyc/2 + 30 Peripheral data hold time, MCU read of ports Delay time, peripheral data write, MCU write to ports Symbol Min fo tcyc tPDSU tPDH tPWD dc 125 102 0 -- Max 8.0 -- -- -- 40 MHz ns ns ns ns Unit MCU READ OF PORT ECLK tPDSU PORTS tPDH Figure 18-6. Port Read Timing Diagram MCU WRITE TO PORT ECLK tPWD PORT A PREVIOUS PORT DATA NEW DATA VALID Figure 18-7. Port Write Timing Diagram Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 333 Electrical Characteristics 18.14 Non-Multiplexed Expansion Bus Timing Num Characteristic(1), (2) Delay -- tcyc = 1/fo Symbol fo tcyc 5 MHz Min dc 125 60 60 -- 20 0 30 0 -- 20 30 -- 20 20 -- 11 20 -- -- -- -- 0 36 Max 8.0 -- -- -- 60 -- -- -- -- 46 -- -- 49 -- -- 49 -- -- 35 30 60 65 10 -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Frequency of operation (E-clock frequency) 1 2 3 5 6 7 11 12 13 14 15 16 17 18 19 20 21 22 23 26 27 28 29 Cycle time Pulse width, E low Pulse width, E high(3) Address delay time Address hold time Address valid time to E rise Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(3) Read/write delay timw Read/write valid time to E rise Read/write hold time Low strobe delay time Low strobe valid time to E rise Low strobe hold time Address access time(3) Access time from E rise(3) Chip-select delay time Chip-select access time(3) Chip-select hold time Chip-select negated time tCSN = tcyc/4 + delay tACCA = tcyc-tAD-tDSR tACCE = PWEH-tDSR tCSD = tcyc/4 + delay tACCS = tcyc-tCSD-tDSR tLSD = tcyc/4 + delay tLSV = PWEL-tLSD tDSW = PWEH-tDDW tRWD = tcyc/4 + delay tRWV = PWEL-tRWD tDDW = tcyc/4 + delay tAV = PWEL-tAD PWEL = tcyc/2 + delay PWEH = tcyc/2 + delay tAD = tcyc/4 + delay -2 -2 29 -- -- -- -- 25 -- -- 18 -- -- 18 -- -- -- -- 29 -- -- 5 PWEL PWEH tAD tAH tAV tDSR tDHR tDDW tDHW tDSW tRWD tRWV tRWH tLSD tLSV tLSH tACCA tACCE tCSD tACCS tCSH tCSN 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted 2. All timings are calculated for normal port drives. 3. This characteristic is affected by clock stretch. Add N x tcyc where N = 0, 1, 2, or 3, depending on the number of clock stretches. MC68HC812A4 -- Rev. 3.0 334 Electrical Characteristics Advance Information MOTOROLA Electrical Characteristics Non-Multiplexed Expansion Bus Timing 1 2 ECLK 22 7 5 ADDR[15:0] 6 3 23 DATA[15:0] READ 11 12 13 DATA[15:0] WRITE 15 14 16 R/W 17 18 19 LSTRB (W/O TAG ENABLED) 20 21 29 26 CS 27 28 Note: Measurement points shown are 20% and 70% of VDD. Figure 18-8. Non-Multiplexed Expansion Bus Timing Diagram Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 335 Electrical Characteristics 18.15 SPI Timing Num Function(1), Operating frequency Master Slave 1 SCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high or low time Master Slave Sequential transfer delay Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output (2) Symbol fop Min DC DC 2 2 1/2 1 1/2 1 tcyc - 60 tcyc - 30 1/2 1 30 30 0 30 -- -- -- -- 0 0 -- -- -- -- Max 1/2 1/2 256 -- -- -- -- -- 128 tcyc -- -- -- -- -- -- -- 1 1 50 50 -- -- tcyc - 30 30 tcyc - 30 30 Unit E-clock frequency tcyc tsck 2 tLead tsck tcyc tsck tcyc ns 3 tLag 4 twsck 5 ttd tsck tcyc ns 6 tsu 7 8 9 10 thi ta tdis tv ns tcyc tcyc ns 11 tho ns 12 tri tro tfi tfo ns ns ns ns 13 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, 200 pF load on all SPI pins 2. All AC timing is shown with respect to 20% VDD and 70% VDD levels, unless otherwise noted. MC68HC812A4 -- Rev. 3.0 336 Electrical Characteristics Advance Information MOTOROLA Electrical Characteristics SPI Timing SS(1) OUTPUT 5 2 SCK CPOL = 0 (OUTPUT SCK CPOL = 1 OUTPUT 6 MISO INPUT 10 MOSI OUTPUT MSB OUT(2) 7 MSB IN(2) BIT 6 . . . 1 10 BIT 6 . . . 1 LSB OUT LSB IN 11 1 4 4 13 12 3 Notes: 1. SS output mode (DDS7 = 1, SSOE = 1) 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB A) SPI Master Timing (CPHA = 0) SS(1) OUTPUT 1 2 SCK CPOL = 0 OUTPUT 4 SCK CPOL = 1 OUTPUT 6 MISO INPUT 10 MOSI OUTPUT PORT DATA MASTER MSB OUT(2) MSB IN(2) 7 BIT 6 . . . 1 11 BIT 6 . . . 1 MASTER LSB OUT LSB IN 4 12 13 13 12 3 5 PORT DATA Notes: 1. SS output mode (DDS7 = 1, SSOE = 1) 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB B) SPI Master Timing (CPHA = 1) Figure 18-9. SPI Timing Diagram (1 of 2) Advance Information MOTOROLA Electrical Characteristics MC68HC812A4 -- Rev. 3.0 337 Electrical Characteristics SS INPUT 5 1 SCK CPOL = 0 INPUT 2 SCK CPOL = 1 INPUT 8 MISO OUTPUT SLAVE 6 MOSI INPUT MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 10 BIT 6 . . . 1 4 4 12 13 9 11 11 SEE NOTE 13 12 3 SLAVE LSB OUT Note: Not defined but normally MSB of character just received A) SPI Slave Timing (CPHA = 0) SS INPUT 1 2 SCK CPOL = 0 INPUT 4 SCK CPOL = 1 INPUT 10 MISO OUTPUT SEE NOTE 8 MOSI INPUT SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 4 12 13 13 12 3 5 11 BIT 6 . . . 1 SLAVE LSB OUT 9 Note: Not defined but normally LSB of character just received B) SPI Slave Timing (CPHA = 1) Figure 18-9. SPI Timing Diagram (2 of 2) MC68HC812A4 -- Rev. 3.0 338 Electrical Characteristics Advance Information MOTOROLA Advance Information -- MC68HC812A4 Section 19. Mechanical Specifications 19.1 Contents 19.2 19.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 112-Pin Low-Profile Quad Flat Pack (Case 987) . . . . . . . . . .340 19.2 Introduction This section provides dimensions for the 112-lead low-profile quad flat pack (LQFP). The diagram included in this section shows the latest information at the time of this publication. To make sure that you have the latest package specifications, contact one of these sources: * * Local Motorola Sales Office Motorola Fax Back System (MfaxTM) - Phone 1-602-244-6609 - EMAIL RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/ * Worldwide Web (wwweb) home page at http://motorola.com/sps/ Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications. Mfax is a trademark of Motorola, Inc. Advance Information MOTOROLA Mechanical Specifications MC68HC812A4 -- Rev. 3.0 339 Mechanical Specifications 19.3 112-Pin Low-Profile Quad Flat Pack (Case 987) 4X PIN 1 IDENT 1 112 0.20 T L-M N 4X 28 TIPS 85 84 0.20 T L-M N J1 J1 C L 4X P VIEW Y 108X G X X=L, M OR N VIEW Y B L M B1 V1 V J AA 28 57 F D 0.13 M T L-M N ROTATED 90 COUNTERCLOCKWISE BASE METAL 29 56 N A1 S1 A S SECTION J1-J1 C2 C 0.050 2 VIEW AB 0.10 T 112X SEATING PLANE NOTES: 1. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. 3 T DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3 MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 0 8 3 7 11 13 11 13 R R2 0.25 GAGE PLANE R R1 C1 (Y) (Z) VIEW AB (K) E 1 MC68HC812A4 -- Rev. 3.0 340 Mechanical Specifications Advance Information MOTOROLA Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447. Customer Focus Center, 1-800-521-6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-8573 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 MfaxTM, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ Mfax is a trademark of Motorola, Inc. (c) Motorola, Inc., 1999 MC68HC812A4/D |
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